diff options
| author | Rishi-k-s <rishikrishna.sr@gmail.com> | 2025-04-27 00:13:59 +0530 |
|---|---|---|
| committer | Rishi-k-s <rishikrishna.sr@gmail.com> | 2025-04-27 00:13:59 +0530 |
| commit | eb84a4c4657ad9820cba87d72f895318e7360e81 (patch) | |
| tree | daf42242a9b8cd6e11ff15d6c848514b04d8f600 | |
110 files changed, 6466 insertions, 0 deletions
diff --git a/basic_led.cache/wt/project.wpc b/basic_led.cache/wt/project.wpc new file mode 100644 index 0000000..0a638ea --- /dev/null +++ b/basic_led.cache/wt/project.wpc @@ -0,0 +1,4 @@ +version:1 +57656254616c6b5472616e736d697373696f6e417474656d70746564:2 +6d6f64655f636f756e7465727c4755494d6f6465:1 +eof: diff --git a/basic_led.cache/wt/synthesis.wdf b/basic_led.cache/wt/synthesis.wdf new file mode 100644 index 0000000..23b3689 --- /dev/null +++ b/basic_led.cache/wt/synthesis.wdf @@ -0,0 +1,52 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:786337613335746370673233362d31:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:746f70:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d7668646c5f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e737472736574:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 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+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313973:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313832352e3838334d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:313135382e3539344d42:00:00 +eof:1658202126 diff --git a/basic_led.cache/wt/synthesis_details.wdf b/basic_led.cache/wt/synthesis_details.wdf new file mode 100644 index 0000000..78f8d66 --- /dev/null +++ b/basic_led.cache/wt/synthesis_details.wdf @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git a/basic_led.cache/wt/webtalk_pa.xml b/basic_led.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..2f960c1 --- /dev/null +++ b/basic_led.cache/wt/webtalk_pa.xml @@ -0,0 +1,21 @@ +<?xml version="1.0" encoding="UTF-8" ?> +<document> +<!--The data in this file is primarily intended for consumption by Xilinx tools. +The structure and the elements are likely to change over the next few releases. +This means code written to parse this file will need to be revisited each subsequent release.--> +<application name="pa" timeStamp="Sat Apr 26 17:41:43 2025"> +<section name="Project Information" visible="false"> +<property name="ProjectID" value="0cc612c26cb9434e839c1e1f43cc38b7" type="ProjectID"/> +<property name="ProjectIteration" value="5" type="ProjectIteration"/> +</section> +<section name="PlanAhead Usage" visible="true"> +<item name="Project Data"> +<property name="SrcSetCount" value="1" type="SrcSetCount"/> +<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/> +<property name="DesignMode" value="RTL" type="DesignMode"/> +<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/> +<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/> +</item> +</section> +</application> +</document> diff --git a/basic_led.hw/basic_led.lpr b/basic_led.hw/basic_led.lpr new file mode 100644 index 0000000..b81b976 --- /dev/null +++ b/basic_led.hw/basic_led.lpr @@ -0,0 +1,9 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2024.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. --> + +<labtools version="1" minor="0"> + <HWSession Dir="hw_1" File="hw.xml"/> +</labtools> diff --git a/basic_led.hw/hw_1/hw.xml b/basic_led.hw/hw_1/hw.xml new file mode 100644 index 0000000..5c229fb --- /dev/null +++ b/basic_led.hw/hw_1/hw.xml @@ -0,0 +1,18 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2024.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. --> + +<hwsession version="1" minor="2"> + <device name="xc7a35t_0" gui_info=""/> + <ObjectList object_type="hw_device" gui_info=""> + <Object name="xc7a35t_0" gui_info=""> + <Properties Property="FULL_PROBES.FILE" value=""/> + <Properties Property="PROBES.FILE" value=""/> + <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/top.bit"/> + <Properties Property="SLR.COUNT" value="1"/> + </Object> + </ObjectList> + <probeset name="hw project" active="false"/> +</hwsession> diff --git a/basic_led.runs/.jobs/vrs_config_1.xml b/basic_led.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..44b13ae --- /dev/null +++ b/basic_led.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/> + </Parameters> + <ProductInfo Name="vivado"/> +</Runs> + diff --git a/basic_led.runs/.jobs/vrs_config_2.xml b/basic_led.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..44b13ae --- /dev/null +++ b/basic_led.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/> + </Parameters> + <ProductInfo Name="vivado"/> +</Runs> + diff --git a/basic_led.runs/.jobs/vrs_config_3.xml b/basic_led.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..65bdc33 --- /dev/null +++ b/basic_led.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="impl_1" LaunchDir="D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/> + </Parameters> + <ProductInfo Name="vivado"/> +</Runs> + diff --git a/basic_led.runs/.jobs/vrs_config_4.xml b/basic_led.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..6849204 --- /dev/null +++ b/basic_led.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="impl_1" LaunchDir="D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/> + </Parameters> + <ProductInfo Name="vivado"/> +</Runs> + diff --git a/basic_led.runs/.jobs/vrs_config_5.xml b/basic_led.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..44b13ae --- /dev/null +++ b/basic_led.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/> + </Parameters> + <ProductInfo Name="vivado"/> +</Runs> + diff --git a/basic_led.runs/.jobs/vrs_config_6.xml b/basic_led.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..65bdc33 --- /dev/null +++ b/basic_led.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="impl_1" LaunchDir="D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/> + </Parameters> + <ProductInfo Name="vivado"/> +</Runs> + diff --git a/basic_led.runs/.jobs/vrs_config_7.xml b/basic_led.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..44b13ae --- /dev/null +++ b/basic_led.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="synth_1" LaunchDir="D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/> + </Parameters> + <ProductInfo Name="vivado"/> +</Runs> + diff --git a/basic_led.runs/.jobs/vrs_config_8.xml b/basic_led.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..65bdc33 --- /dev/null +++ b/basic_led.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="impl_1" LaunchDir="D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/> + </Parameters> + <ProductInfo Name="vivado"/> +</Runs> + diff --git a/basic_led.runs/.jobs/vrs_config_9.xml b/basic_led.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..6849204 --- /dev/null +++ b/basic_led.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,11 @@ +<?xml version="1.0"?> +<Runs Version="1" Minor="0"> + <Run Id="impl_1" LaunchDir="D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/> + <Parameters> + <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/> + <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/> + <Parameter Name="general.shortenLongPath" Val="true" Type="bool"/> + </Parameters> + <ProductInfo Name="vivado"/> +</Runs> + diff --git a/basic_led.runs/impl_1/.Vivado_Implementation.queue.rst b/basic_led.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/basic_led.runs/impl_1/.Vivado_Implementation.queue.rst diff --git a/basic_led.runs/impl_1/.init_design.begin.rst b/basic_led.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000..77ff48f --- /dev/null +++ b/basic_led.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ +<?xml version="1.0"?> +<ProcessHandle Version="1" Minor="0"> + <Process Command=".planAhead." Owner="rishi" Host="RISHITUF" Pid="22200"> + </Process> +</ProcessHandle> diff --git a/basic_led.runs/impl_1/.init_design.end.rst b/basic_led.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/basic_led.runs/impl_1/.init_design.end.rst diff --git a/basic_led.runs/impl_1/.opt_design.begin.rst b/basic_led.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000..77ff48f --- /dev/null +++ b/basic_led.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ +<?xml version="1.0"?> +<ProcessHandle Version="1" Minor="0"> + <Process Command=".planAhead." Owner="rishi" Host="RISHITUF" Pid="22200"> + </Process> +</ProcessHandle> diff --git a/basic_led.runs/impl_1/.opt_design.end.rst b/basic_led.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/basic_led.runs/impl_1/.opt_design.end.rst diff --git a/basic_led.runs/impl_1/.phys_opt_design.begin.rst b/basic_led.runs/impl_1/.phys_opt_design.begin.rst new file mode 100644 index 0000000..77ff48f --- /dev/null +++ b/basic_led.runs/impl_1/.phys_opt_design.begin.rst @@ -0,0 +1,5 @@ +<?xml version="1.0"?> +<ProcessHandle Version="1" Minor="0"> + <Process Command=".planAhead." Owner="rishi" Host="RISHITUF" Pid="22200"> + </Process> +</ProcessHandle> diff --git a/basic_led.runs/impl_1/.phys_opt_design.end.rst b/basic_led.runs/impl_1/.phys_opt_design.end.rst new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/basic_led.runs/impl_1/.phys_opt_design.end.rst diff --git a/basic_led.runs/impl_1/.place_design.begin.rst b/basic_led.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000..77ff48f --- /dev/null +++ b/basic_led.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ +<?xml version="1.0"?> +<ProcessHandle Version="1" Minor="0"> + <Process Command=".planAhead." Owner="rishi" Host="RISHITUF" Pid="22200"> + </Process> +</ProcessHandle> diff --git a/basic_led.runs/impl_1/.place_design.end.rst b/basic_led.runs/impl_1/.place_design.end.rst new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/basic_led.runs/impl_1/.place_design.end.rst diff --git a/basic_led.runs/impl_1/.route_design.begin.rst b/basic_led.runs/impl_1/.route_design.begin.rst new file mode 100644 index 0000000..77ff48f --- /dev/null +++ b/basic_led.runs/impl_1/.route_design.begin.rst @@ -0,0 +1,5 @@ +<?xml version="1.0"?> +<ProcessHandle Version="1" Minor="0"> + <Process Command=".planAhead." Owner="rishi" Host="RISHITUF" Pid="22200"> + </Process> +</ProcessHandle> diff --git a/basic_led.runs/impl_1/.route_design.end.rst b/basic_led.runs/impl_1/.route_design.end.rst new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/basic_led.runs/impl_1/.route_design.end.rst diff --git a/basic_led.runs/impl_1/.vivado.begin.rst b/basic_led.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000..c8a847b --- /dev/null +++ b/basic_led.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,25 @@ +<?xml version="1.0"?> +<ProcessHandle Version="1" Minor="0"> + <Process Command="vivado.bat" Owner="rishi" Host="RISHITUF" Pid="21676" HostCore="16" HostMemory="016777072640"> + </Process> +</ProcessHandle> +<?xml version="1.0"?> +<ProcessHandle Version="1" Minor="0"> + <Process Command="vivado.bat" Owner="rishi" Host="RISHITUF" Pid="15864" HostCore="16" HostMemory="016777072640"> + </Process> +</ProcessHandle> +<?xml version="1.0"?> +<ProcessHandle Version="1" Minor="0"> + <Process Command="vivado.bat" Owner="rishi" Host="RISHITUF" Pid="29332" HostCore="16" HostMemory="016777072640"> + </Process> +</ProcessHandle> +<?xml version="1.0"?> +<ProcessHandle Version="1" Minor="0"> + <Process Command="vivado.bat" Owner="rishi" Host="RISHITUF" Pid="3896" HostCore="16" HostMemory="016777072640"> + </Process> +</ProcessHandle> +<?xml version="1.0"?> +<ProcessHandle Version="1" Minor="0"> + <Process Command="vivado.bat" Owner="rishi" Host="RISHITUF" Pid="28120" HostCore="16" HostMemory="016777072640"> + </Process> +</ProcessHandle> diff --git a/basic_led.runs/impl_1/.vivado.end.rst b/basic_led.runs/impl_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/basic_led.runs/impl_1/.vivado.end.rst diff --git a/basic_led.runs/impl_1/.write_bitstream.begin.rst b/basic_led.runs/impl_1/.write_bitstream.begin.rst new file mode 100644 index 0000000..989a9be --- /dev/null +++ b/basic_led.runs/impl_1/.write_bitstream.begin.rst @@ -0,0 +1,5 @@ +<?xml version="1.0"?> +<ProcessHandle Version="1" Minor="0"> + <Process Command=".planAhead." Owner="rishi" Host="RISHITUF" Pid="14724"> + </Process> +</ProcessHandle> diff --git a/basic_led.runs/impl_1/.write_bitstream.end.rst b/basic_led.runs/impl_1/.write_bitstream.end.rst new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/basic_led.runs/impl_1/.write_bitstream.end.rst diff --git a/basic_led.runs/impl_1/ISEWrap.js b/basic_led.runs/impl_1/ISEWrap.js new file mode 100644 index 0000000..61806d0 --- /dev/null +++ b/basic_led.runs/impl_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) { + if ( ISEScriptArgs(loopi) == "-quiet" ) { + ISELogEcho = false; + break; + } + } + + // 4. WSH version check + var ISEOptimalVersionWSH = 5.6; + var ISECurrentVersionWSH = WScript.Version; + if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) { + + ISEStdErr( "" ); + ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " + + ISEOptimalVersionWSH + " or higher. Downloads" ); + ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " ); + ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" ); + ISEStdErr( "" ); + + ISEOldVersionWSH = true; + } + +} + +function ISEStep( ISEProg, ISEArgs ) { + + // CHECK for a STOP FILE + if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) { + ISEStdErr( "" ); + ISEStdErr( "*** Halting run - EA reset detected ***" ); + ISEStdErr( "" ); + WScript.Quit( 1 ); + } + + // WRITE STEP HEADER to LOG + ISEStdOut( "" ); + ISEStdOut( "*** Running " + ISEProg ); + ISEStdOut( " with args " + ISEArgs ); + ISEStdOut( "" ); + + // LAUNCH! + var ISEExitCode = ISEExec( ISEProg, ISEArgs ); + if ( ISEExitCode != 0 ) { + WScript.Quit( ISEExitCode ); + } + +} + +function ISEExec( ISEProg, ISEArgs ) { + + var ISEStep = ISEProg; + if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") { + ISEProg += ".bat"; + } + + var ISECmdLine = ISEProg + " " + ISEArgs; + var ISEExitCode = 1; + + if ( ISEOldVersionWSH ) { // WSH 5.1 + + // BEGIN file creation + ISETouchFile( ISEStep, "begin" ); + + // LAUNCH! + ISELogFileStr.Close(); + ISECmdLine = + "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" ); + ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" ); + ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg + + "\" Owner=\"" + ISEUser + + "\" Host=\"" + ISEHost + + "\" Pid=\"" + ISEPid + + "\" HostCore=\"" + ISEHOSTCORE + + "\" HostMemory=\"" + ISEMEMTOTAL + + "\">" ); + ISEBeginFile.WriteLine( " </Process>" ); + ISEBeginFile.WriteLine( "</ProcessHandle>" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/basic_led.runs/impl_1/ISEWrap.sh b/basic_led.runs/impl_1/ISEWrap.sh new file mode 100644 index 0000000..05d5381 --- /dev/null +++ b/basic_led.runs/impl_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE +echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE +echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE +echo " </Process>" >> $ISE_BEGINFILE +echo "</ProcessHandle>" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/basic_led.runs/impl_1/clockInfo.txt b/basic_led.runs/impl_1/clockInfo.txt new file mode 100644 index 0000000..b730da9 --- /dev/null +++ b/basic_led.runs/impl_1/clockInfo.txt @@ -0,0 +1,10 @@ +------------------------------------- +| Tool Version : Vivado v.2024.2 +| Date : Sat Apr 26 17:40:54 2025 +| Host : rishiTUF +| Design : design_1 +| Device : xc7a35t-cpg236-1-- +------------------------------------- + +For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US + diff --git a/basic_led.runs/impl_1/gen_run.xml b/basic_led.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..0dd0b07 --- /dev/null +++ b/basic_led.runs/impl_1/gen_run.xml @@ -0,0 +1,142 @@ +<?xml version="1.0" encoding="UTF-8"?> +<GenRun Id="impl_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1745669427"> + <File Type="PA-TCL" Name="top.tcl"/> + <File Type="REPORTS-TCL" Name="top_reports.tcl"/> + <File Type="INIT-TIMING" Name="top_timing_summary_init.rpt"/> + <File Type="OPT-DCP" Name="top_opt.dcp"/> + <File Type="OPT-DRC" Name="top_drc_opted.rpt"/> + <File Type="OPT-METHODOLOGY-DRC" Name="top_methodology_drc_opted.rpt"/> + <File Type="OPT-HWDEF" Name="top.hwdef"/> + <File Type="OPT-TIMING" Name="top_timing_summary_opted.rpt"/> + <File Type="OPT-RQA-PB" Name="top_rqa_opted.pb"/> + <File Type="PWROPT-DCP" Name="top_pwropt.dcp"/> + <File Type="PWROPT-DRC" Name="top_drc_pwropted.rpt"/> + <File Type="PWROPT-TIMING" Name="top_timing_summary_pwropted.rpt"/> + <File Type="PLACE-DCP" Name="top_placed.dcp"/> + <File Type="PLACE-IO" Name="top_io_placed.rpt"/> + <File Type="PLACE-CLK" Name="top_clock_utilization_placed.rpt"/> + <File Type="PLACE-UTIL" Name="top_utilization_placed.rpt"/> + <File Type="PLACE-UTIL-PB" Name="top_utilization_placed.pb"/> + <File Type="PLACE-CTRL" Name="top_control_sets_placed.rpt"/> + <File Type="PLACE-SIMILARITY" Name="top_incremental_reuse_placed.rpt"/> + <File Type="PLACE-PRE-SIMILARITY" Name="top_incremental_reuse_pre_placed.rpt"/> + <File Type="PLACE-TIMING" Name="top_timing_summary_placed.rpt"/> + <File Type="PLACE-RQA-PB" Name="top_rqa_placed.pb"/> + <File Type="POSTPLACE-PWROPT-DCP" Name="top_postplace_pwropt.dcp"/> + <File Type="POSTPLACE-PWROPT-TIMING" Name="top_timing_summary_postplace_pwropted.rpt"/> + <File Type="PHYSOPT-DCP" Name="top_physopt.dcp"/> + <File Type="PHYSOPT-DRC" Name="top_drc_physopted.rpt"/> + <File Type="PHYSOPT-TIMING" Name="top_timing_summary_physopted.rpt"/> + <File Type="ROUTE-ERROR-DCP" Name="top_routed_error.dcp"/> + <File Type="ROUTE-DCP" Name="top_routed.dcp"/> + <File Type="ROUTE-BLACKBOX-DCP" Name="top_routed_bb.dcp"/> + <File Type="ROUTE-DRC" Name="top_drc_routed.rpt"/> + <File Type="ROUTE-DRC-PB" Name="top_drc_routed.pb"/> + <File Type="ROUTE-DRC-RPX" Name="top_drc_routed.rpx"/> + <File Type="ROUTE-METHODOLOGY-DRC" Name="top_methodology_drc_routed.rpt"/> + <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="top_methodology_drc_routed.rpx"/> + <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="top_methodology_drc_routed.pb"/> + <File Type="ROUTE-PWR" Name="top_power_routed.rpt"/> + <File Type="ROUTE-PWR-SUM" Name="top_power_summary_routed.pb"/> + <File Type="ROUTE-PWR-RPX" Name="top_power_routed.rpx"/> + <File Type="ROUTE-STATUS" Name="top_route_status.rpt"/> + <File Type="ROUTE-STATUS-PB" Name="top_route_status.pb"/> + <File Type="ROUTE-TIMINGSUMMARY" Name="top_timing_summary_routed.rpt"/> + <File Type="ROUTE-TIMING-PB" Name="top_timing_summary_routed.pb"/> + <File Type="ROUTE-TIMING-RPX" Name="top_timing_summary_routed.rpx"/> + <File Type="ROUTE-SIMILARITY" Name="top_incremental_reuse_routed.rpt"/> + <File Type="ROUTE-CLK" Name="top_clock_utilization_routed.rpt"/> + <File Type="ROUTE-BUS-SKEW" Name="top_bus_skew_routed.rpt"/> + <File Type="ROUTE-BUS-SKEW-PB" Name="top_bus_skew_routed.pb"/> + <File Type="ROUTE-BUS-SKEW-RPX" Name="top_bus_skew_routed.rpx"/> + <File Type="ROUTE-RQS-PB" Name="top_rqs_routed.pb"/> + <File Type="POSTROUTE-PHYSOPT-DCP" Name="top_postroute_physopt.dcp"/> + <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="top_postroute_physopt_bb.dcp"/> + <File Type="POSTROUTE-PHYSOPT-TIMING" Name="top_timing_summary_postroute_physopted.rpt"/> + <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="top_timing_summary_postroute_physopted.pb"/> + <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="top_timing_summary_postroute_physopted.rpx"/> + <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="top_bus_skew_postroute_physopted.rpt"/> + <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="top_bus_skew_postroute_physopted.pb"/> + <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="top_bus_skew_postroute_physopted.rpx"/> + <File Type="BG-BIT" Name="top.bit"/> + <File Type="BG-BIN" Name="top.bin"/> + <File Type="BITSTR-MSK" Name="top.msk"/> + <File Type="BITSTR-RBT" Name="top.rbt"/> + <File Type="BITSTR-NKY" Name="top.nky"/> + <File Type="BITSTR-BMM" Name="top_bd.bmm"/> + <File Type="BITSTR-MMI" Name="top.mmi"/> + <File Type="PDI-FILE" Name="top.pdi"/> + <File Type="BOOT-PDI-FILE" Name="top_boot.pdi"/> + <File Type="PL-PDI-FILE" Name="top_pld.pdi"/> + <File Type="RCFI_FILE" Name="top.rcfi"/> + <File Type="CFI_FILE" Name="top.cfi"/> + <File Type="RNPI_FILE" Name="top.rnpi"/> + <File Type="NPI_FILE" Name="top.npi"/> + <File Type="RBD_FILE" Name="top.rbd"/> + <File Type="BITSTR-LTX" Name="debug_nets.ltx"/> + <File Type="BITSTR-LTX" Name="top.ltx"/> + <File Type="BITSTR-SYSDEF" Name="top.sysdef"/> + <File Type="BG-BGN" Name="top.bgn"/> + <File Type="BG-DRC" Name="top.drc"/> + <File Type="RDI-RDI" Name="top.vdi"/> + <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/> + <File Type="ROUTE-RQS" Name="top_routed.rqs"/> + <File Type="POSTROUTE-PHYSOPT-RQS" Name="top_postroute_physopted.rqs"/> + <File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/> + <File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/> + <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sources_1/new/top.v"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="top"/> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> + <Filter Type="Constrs"/> + <File Path="$PSRCDIR/constrs_1/new/switches_leds_constarins.xdc"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + </FileInfo> + </File> + <Config> + <Option Name="ConstrsType" Val="XDC"/> + </Config> + </FileSet> + <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> + <Filter Type="Utils"/> + <File Path="$PSRCDIR/utils_1/imports/synth_1/top.dcp"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedInSteps" Val="synth_1"/> + <Attr Name="AutoDcp" Val="1"/> + </FileInfo> + </File> + <Config> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"> + <Desc>Default settings for Implementation.</Desc> + </StratHandle> + <Step Id="init_design"/> + <Step Id="opt_design"/> + <Step Id="power_opt_design"/> + <Step Id="place_design"/> + <Step Id="post_place_power_opt_design"/> + <Step Id="phys_opt_design"/> + <Step Id="route_design"/> + <Step Id="post_route_phys_opt_design"/> + <Step Id="write_bitstream"/> + </Strategy> +</GenRun> diff --git a/basic_led.runs/impl_1/htr.txt b/basic_led.runs/impl_1/htr.txt new file mode 100644 index 0000000..5b5881b --- /dev/null +++ b/basic_led.runs/impl_1/htr.txt @@ -0,0 +1,10 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +REM + +vivado -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace diff --git a/basic_led.runs/impl_1/init_design.pb b/basic_led.runs/impl_1/init_design.pb Binary files differnew file mode 100644 index 0000000..bc84aab --- /dev/null +++ b/basic_led.runs/impl_1/init_design.pb diff --git a/basic_led.runs/impl_1/opt_design.pb b/basic_led.runs/impl_1/opt_design.pb Binary files differnew file mode 100644 index 0000000..760b60d --- /dev/null +++ b/basic_led.runs/impl_1/opt_design.pb diff --git a/basic_led.runs/impl_1/phys_opt_design.pb b/basic_led.runs/impl_1/phys_opt_design.pb Binary files differnew file mode 100644 index 0000000..e7dcc5a --- /dev/null +++ b/basic_led.runs/impl_1/phys_opt_design.pb diff --git a/basic_led.runs/impl_1/place_design.pb b/basic_led.runs/impl_1/place_design.pb Binary files differnew file mode 100644 index 0000000..41adfa4 --- /dev/null +++ b/basic_led.runs/impl_1/place_design.pb diff --git a/basic_led.runs/impl_1/project.wdf b/basic_led.runs/impl_1/project.wdf new file mode 100644 index 0000000..7e4d6ea --- /dev/null +++ b/basic_led.runs/impl_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6239663732653931616461373438353561373136613632656165333934353835:506172656e742050412070726f6a656374204944:00 +eof:2383876863 diff --git a/basic_led.runs/impl_1/route_design.pb b/basic_led.runs/impl_1/route_design.pb Binary files differnew file mode 100644 index 0000000..1035cab --- /dev/null +++ b/basic_led.runs/impl_1/route_design.pb diff --git a/basic_led.runs/impl_1/rundef.js b/basic_led.runs/impl_1/rundef.js new file mode 100644 index 0000000..276c05d --- /dev/null +++ b/basic_led.runs/impl_1/rundef.js @@ -0,0 +1,41 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Vitis/2024.2/bin;D:/Vivado/2024.2/ids_lite/ISE/bin/nt64;D:/Vivado/2024.2/ids_lite/ISE/lib/nt64;D:/Vivado/2024.2/bin;"; +} else { + PathVal = "D:/Vitis/2024.2/bin;D:/Vivado/2024.2/ids_lite/ISE/bin/nt64;D:/Vivado/2024.2/ids_lite/ISE/lib/nt64;D:/Vivado/2024.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "write_bitstream", "begin" ); +ISEStep( "vivado", + "-log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/basic_led.runs/impl_1/runme.bat b/basic_led.runs/impl_1/runme.bat new file mode 100644 index 0000000..6733dc9 --- /dev/null +++ b/basic_led.runs/impl_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/basic_led.runs/impl_1/runme.log b/basic_led.runs/impl_1/runme.log new file mode 100644 index 0000000..ee29d81 --- /dev/null +++ b/basic_led.runs/impl_1/runme.log @@ -0,0 +1,694 @@ + +*** Running vivado + with args -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace + + + +****** Vivado v2024.2 (64-bit) + **** SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024 + **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 + **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 + **** Start of session at: Sat Apr 26 17:40:35 2025 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source top.tcl -notrace +create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 656.090 ; gain = 226.457 +Command: link_design -top top -part xc7a35tcpg236-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 843.078 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2024.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc] +Finished Parsing XDC File [D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 969.918 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +5 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.335 . Memory (MB): peak = 992.352 ; gain = 18.375 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1477.633 ; gain = 485.281 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 1 Initialization | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 2 Timer Update And Timing Data Collection | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3 Retarget +INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 +INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Retarget | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Constant propagation | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 5 Sweep +INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 5 Sweep | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Sweep | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1879.738 ; gain = 0.000 +BUFG optimization | Checksum: 236c74c94 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Shift Register Optimization | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 8 Post Processing Netlist +Phase 8 Post Processing Netlist | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Post Processing Netlist | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Phase 9 Finalization + +Phase 9.1 Finalizing Design Cores and Updating Shapes +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 9.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 9.2 Verifying Netlist Connectivity | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 9 Finalization | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1879.738 ; gain = 905.762 +INFO: [Vivado 12-24828] Executing command : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx +Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Vivado/2024.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_drc_opted.rpt. +report_drc completed successfully +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1879.738 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_opt.dcp' has been generated. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1cfab23ea + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1cfab23ea + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.4 Global Place Phase1 +Phase 2.4 Global Place Phase1 | Checksum: 229d9fc97 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.202 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.5 Global Place Phase2 +WARNING: [Place 46-29] Timing had been disabled during Placer and, therefore, physical synthesis in Placer will be skipped. +Phase 2.5 Global Place Phase2 | Checksum: 1fdc50950 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.224 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 1fdc50950 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.225 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1fdc50950 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.225 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 218f9ec8d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.227 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 23324120f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.231 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 23324120f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.400 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.400 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.401 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.401 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.415 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.417 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 1x1| 1x1| +|___________|___________________|___________________| +| South| 1x1| 1x1| +|___________|___________________|___________________| +| East| 1x1| 1x1| +|___________|___________________|___________________| +| West| 1x1| 1x1| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.417 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 4.3 Placer Reporting | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.417 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.417 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.418 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Ending Placer Task | Checksum: 18f80c67c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.418 . Memory (MB): peak = 1879.738 ; gain = 0.000 +44 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel. +Running report generation with 2 threads. +INFO: [Vivado 12-24828] Executing command : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb +INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file top_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 +INFO: [Vivado 12-24828] Executing command : report_io -file top_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1886.414 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1886.414 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_placed.dcp' has been generated. +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' + +Starting Initial Update Timing Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1886.414 ; gain = 0.000 +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +53 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.520 ; gain = 0.027 +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1894.520 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: a9ec6e4c ConstDB: 0 ShapeSum: 4512fbd9 RouteDB: a0815c57 +Post Restoration Checksum: NetGraph: 94020b10 | NumContArr: 37e9989c | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1971.547 ; gain = 77.027 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1977.602 ; gain = 83.082 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1977.602 ; gain = 83.082 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 2 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 2 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 3 Global Routing +Phase 3 Global Routing | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 4 Initial Routing + +Phase 4.1 Initial Net Routing Pass + Number of Nodes with overlaps = 0 +Phase 4.1 Initial Net Routing Pass | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +Phase 4 Initial Routing | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 5 Rip-up And Reroute + +Phase 5.1 Global Iteration 0 +Phase 5.1 Global Iteration 0 | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +Phase 5 Rip-up And Reroute | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 6 Delay and Skew Optimization +Phase 6 Delay and Skew Optimization | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 7 Post Hold Fix + +Phase 7.1 Hold Fix Iter +Phase 7.1 Hold Fix Iter | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +Phase 7 Post Hold Fix | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.000797257 % + Global Horizontal Routing Utilization = 0.000780843 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +--GLOBAL Congestion: +Utilization threshold used for congestion level computation: 0.85 +Congestion Report +North Dir 1x1 Area, Max Cong = 0.900901%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 1.47059%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 8 Route finalize | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 2ce2cc2fa + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 11 Post Process Routing +Phase 11 Post Process Routing | Checksum: 2ce2cc2fa + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +Total Elapsed time in route_design: 11.471 secs + +Phase 12 Post-Route Event Processing +Phase 12 Post-Route Event Processing | Checksum: c68260c9 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +INFO: [Route 35-16] Router Completed Successfully +Ending Routing Task | Checksum: c68260c9 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +60 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +INFO: [Vivado 12-24828] Executing command : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx +Command: report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_drc_routed.rpt. +report_drc completed successfully +INFO: [Vivado 12-24828] Executing command : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx +Command: report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Vivado 12-24838] Running report commands "report_incremental_reuse, report_route_status" in parallel. +Running report generation with 2 threads. +INFO: [Vivado 12-24828] Executing command : report_route_status -file top_route_status.rpt -pb top_route_status.pb +INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file top_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [Vivado 12-24828] Executing command : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx +Command: report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +77 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file top_clock_utilization_routed.rpt +INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2022.895 ; gain = 0.035 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2022.895 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_routed.dcp' has been generated. +INFO: [Common 17-206] Exiting Vivado at Sat Apr 26 17:41:08 2025... + +*** Running vivado + with args -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace + + + +****** Vivado v2024.2 (64-bit) + **** SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024 + **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 + **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 + **** Start of session at: Sat Apr 26 17:41:55 2025 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source top.tcl -notrace +Command: open_checkpoint top_routed.dcp +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 844.984 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2024.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Read ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 939.281 ; gain = 0.000 +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +INFO: [Designutils 20-5722] Start Reading Physical Databases. +Reading placement. +Read Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.164 ; gain = 0.000 +Reading placer database... +Read Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1471.164 ; gain = 0.000 +Read PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.164 ; gain = 0.000 +Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.164 ; gain = 0.000 +Reading routing. +Read RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1471.164 ; gain = 0.000 +Read Physdb Files: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1471.164 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1471.164 ; gain = 17.484 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.164 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2024.2 (64-bit) build 5239630 +open_checkpoint: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1471.164 ; gain = 1041.875 +Command: write_bitstream -force top.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Vivado/2024.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado 12-3199] DRC finished with 0 Errors +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./top.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1976.719 ; gain = 505.555 +INFO: [Common 17-206] Exiting Vivado at Sat Apr 26 17:42:16 2025... diff --git a/basic_led.runs/impl_1/runme.sh b/basic_led.runs/impl_1/runme.sh new file mode 100644 index 0000000..fb0e42e --- /dev/null +++ b/basic_led.runs/impl_1/runme.sh @@ -0,0 +1,48 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Vitis/2024.2/bin;D:/Vivado/2024.2/ids_lite/ISE/bin/nt64;D:/Vivado/2024.2/ids_lite/ISE/lib/nt64:D:/Vivado/2024.2/bin +else + PATH=D:/Vitis/2024.2/bin;D:/Vivado/2024.2/ids_lite/ISE/bin/nt64;D:/Vivado/2024.2/ids_lite/ISE/lib/nt64:D:/Vivado/2024.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .write_bitstream.begin.rst +EAStep vivado -log top.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace + + diff --git a/basic_led.runs/impl_1/top.bit b/basic_led.runs/impl_1/top.bit Binary files differnew file mode 100644 index 0000000..c5b4ab1 --- /dev/null +++ b/basic_led.runs/impl_1/top.bit diff --git a/basic_led.runs/impl_1/top.tcl b/basic_led.runs/impl_1/top.tcl new file mode 100644 index 0000000..228390b --- /dev/null +++ b/basic_led.runs/impl_1/top.tcl @@ -0,0 +1,138 @@ +namespace eval ::optrace { + variable script "D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top.tcl" + variable category "vivado_impl" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } elseif { [info exist ::env(HOST)] } { + set host $::env(HOST) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "<?xml version=\"1.0\"?>" + puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">" + puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">" + puts $ch " </Process>" + puts $ch "</ProcessHandle>" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +OPTRACE "impl_1" END { } +} + + +OPTRACE "impl_1" START { ROLLUP_1 } +OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO } +OPTRACE "write_bitstream setup" START { } +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + set_param chipscope.maxJobs 4 + set_param xicom.use_bs_reader 1 + set_param runs.launchOptions { -jobs 8 } + open_checkpoint top_routed.dcp + set_property webtalk.parent_dir D:/verilog_prog/bink/basic_led/basic_led.cache/wt [current_project] +set_property TOP top [current_fileset] +OPTRACE "read constraints: write_bitstream" START { } +OPTRACE "read constraints: write_bitstream" END { } + catch { write_mem_info -force -no_partial_mmi top.mmi } +OPTRACE "write_bitstream setup" END { } +OPTRACE "write_bitstream" START { } + write_bitstream -force top.bit +OPTRACE "write_bitstream" END { } +OPTRACE "write_bitstream misc" START { } +OPTRACE "read constraints: write_bitstream_post" START { } +OPTRACE "read constraints: write_bitstream_post" END { } + catch {write_debug_probes -quiet -force top} + catch {file copy -force top.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + +OPTRACE "write_bitstream misc" END { } +OPTRACE "Phase: Write Bitstream" END { } +OPTRACE "impl_1" END { } diff --git a/basic_led.runs/impl_1/top.vdi b/basic_led.runs/impl_1/top.vdi new file mode 100644 index 0000000..d31df23 --- /dev/null +++ b/basic_led.runs/impl_1/top.vdi @@ -0,0 +1,716 @@ +#----------------------------------------------------------- +# Vivado v2024.2 (64-bit) +# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024 +# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 +# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 +# Start of session at: Sat Apr 26 17:40:35 2025 +# Process ID : 22200 +# Current directory : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1 +# Command line : vivado.exe -log top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace +# Log file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top.vdi +# Journal file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1\vivado.jou +# Running On : rishiTUF +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26100 +# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12650H +# CPU Frequency : 2688 MHz +# CPU Physical cores : 10 +# CPU Logical cores : 16 +# Host memory : 16777 MB +# Swap memory : 15032 MB +# Total Virtual : 31809 MB +# Available Virtual : 9305 MB +#----------------------------------------------------------- +source top.tcl -notrace +create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 656.090 ; gain = 226.457 +Command: link_design -top top -part xc7a35tcpg236-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 843.078 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2024.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc] +Finished Parsing XDC File [D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 969.918 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +5 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.335 . Memory (MB): peak = 992.352 ; gain = 18.375 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1477.633 ; gain = 485.281 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 1 Initialization | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 2 Timer Update And Timing Data Collection | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3 Retarget +INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 +INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Retarget | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Constant propagation | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 5 Sweep +INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 5 Sweep | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Sweep | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1879.738 ; gain = 0.000 +BUFG optimization | Checksum: 236c74c94 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Shift Register Optimization | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 8 Post Processing Netlist +Phase 8 Post Processing Netlist | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Post Processing Netlist | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Phase 9 Finalization + +Phase 9.1 Finalizing Design Cores and Updating Shapes +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 9.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 9.2 Verifying Netlist Connectivity | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 9 Finalization | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1879.738 ; gain = 905.762 +INFO: [Vivado 12-24828] Executing command : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx +Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Vivado/2024.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_drc_opted.rpt. +report_drc completed successfully +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1879.738 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_opt.dcp' has been generated. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1cfab23ea + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1cfab23ea + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.4 Global Place Phase1 +Phase 2.4 Global Place Phase1 | Checksum: 229d9fc97 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.202 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.5 Global Place Phase2 +WARNING: [Place 46-29] Timing had been disabled during Placer and, therefore, physical synthesis in Placer will be skipped. +Phase 2.5 Global Place Phase2 | Checksum: 1fdc50950 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.224 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 1fdc50950 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.225 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1fdc50950 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.225 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 218f9ec8d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.227 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 23324120f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.231 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 23324120f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.400 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.400 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.401 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.401 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.415 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.417 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 1x1| 1x1| +|___________|___________________|___________________| +| South| 1x1| 1x1| +|___________|___________________|___________________| +| East| 1x1| 1x1| +|___________|___________________|___________________| +| West| 1x1| 1x1| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.417 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 4.3 Placer Reporting | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.417 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.417 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.418 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Ending Placer Task | Checksum: 18f80c67c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.418 . Memory (MB): peak = 1879.738 ; gain = 0.000 +44 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel. +Running report generation with 2 threads. +INFO: [Vivado 12-24828] Executing command : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb +INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file top_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 +INFO: [Vivado 12-24828] Executing command : report_io -file top_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1886.414 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1886.414 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_placed.dcp' has been generated. +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' + +Starting Initial Update Timing Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1886.414 ; gain = 0.000 +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +53 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.520 ; gain = 0.027 +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1894.520 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: a9ec6e4c ConstDB: 0 ShapeSum: 4512fbd9 RouteDB: a0815c57 +Post Restoration Checksum: NetGraph: 94020b10 | NumContArr: 37e9989c | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1971.547 ; gain = 77.027 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1977.602 ; gain = 83.082 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1977.602 ; gain = 83.082 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 2 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 2 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 3 Global Routing +Phase 3 Global Routing | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 4 Initial Routing + +Phase 4.1 Initial Net Routing Pass + Number of Nodes with overlaps = 0 +Phase 4.1 Initial Net Routing Pass | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +Phase 4 Initial Routing | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 5 Rip-up And Reroute + +Phase 5.1 Global Iteration 0 +Phase 5.1 Global Iteration 0 | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +Phase 5 Rip-up And Reroute | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 6 Delay and Skew Optimization +Phase 6 Delay and Skew Optimization | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 7 Post Hold Fix + +Phase 7.1 Hold Fix Iter +Phase 7.1 Hold Fix Iter | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +Phase 7 Post Hold Fix | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.000797257 % + Global Horizontal Routing Utilization = 0.000780843 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +--GLOBAL Congestion: +Utilization threshold used for congestion level computation: 0.85 +Congestion Report +North Dir 1x1 Area, Max Cong = 0.900901%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 1.47059%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 8 Route finalize | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 2ce2cc2fa + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 11 Post Process Routing +Phase 11 Post Process Routing | Checksum: 2ce2cc2fa + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +Total Elapsed time in route_design: 11.471 secs + +Phase 12 Post-Route Event Processing +Phase 12 Post-Route Event Processing | Checksum: c68260c9 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +INFO: [Route 35-16] Router Completed Successfully +Ending Routing Task | Checksum: c68260c9 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +60 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +INFO: [Vivado 12-24828] Executing command : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx +Command: report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_drc_routed.rpt. +report_drc completed successfully +INFO: [Vivado 12-24828] Executing command : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx +Command: report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Vivado 12-24838] Running report commands "report_incremental_reuse, report_route_status" in parallel. +Running report generation with 2 threads. +INFO: [Vivado 12-24828] Executing command : report_route_status -file top_route_status.rpt -pb top_route_status.pb +INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file top_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [Vivado 12-24828] Executing command : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx +Command: report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +77 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file top_clock_utilization_routed.rpt +INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2022.895 ; gain = 0.035 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2022.895 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_routed.dcp' has been generated. +INFO: [Common 17-206] Exiting Vivado at Sat Apr 26 17:41:08 2025... +#----------------------------------------------------------- +# Vivado v2024.2 (64-bit) +# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024 +# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 +# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 +# Start of session at: Sat Apr 26 17:41:55 2025 +# Process ID : 14724 +# Current directory : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1 +# Command line : vivado.exe -log top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace +# Log file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top.vdi +# Journal file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1\vivado.jou +# Running On : rishiTUF +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26100 +# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12650H +# CPU Frequency : 2688 MHz +# CPU Physical cores : 10 +# CPU Logical cores : 16 +# Host memory : 16777 MB +# Swap memory : 15032 MB +# Total Virtual : 31809 MB +# Available Virtual : 9479 MB +#----------------------------------------------------------- +source top.tcl -notrace +Command: open_checkpoint top_routed.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 443.699 ; gain = 6.219 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 844.984 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2024.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Read ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 939.281 ; gain = 0.000 +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +INFO: [Designutils 20-5722] Start Reading Physical Databases. +Reading placement. +Read Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.164 ; gain = 0.000 +Reading placer database... +Read Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1471.164 ; gain = 0.000 +Read PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.164 ; gain = 0.000 +Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.164 ; gain = 0.000 +Reading routing. +Read RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1471.164 ; gain = 0.000 +Read Physdb Files: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1471.164 ; gain = 0.000 +Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1471.164 ; gain = 17.484 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1471.164 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2024.2 (64-bit) build 5239630 +open_checkpoint: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1471.164 ; gain = 1041.875 +Command: write_bitstream -force top.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command write_bitstream +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Vivado/2024.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado 12-3199] DRC finished with 0 Errors +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Writing bitstream ./top.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-83] Releasing license: Implementation +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1976.719 ; gain = 505.555 +INFO: [Common 17-206] Exiting Vivado at Sat Apr 26 17:42:16 2025... diff --git a/basic_led.runs/impl_1/top_21544.backup.vdi b/basic_led.runs/impl_1/top_21544.backup.vdi new file mode 100644 index 0000000..5eb6f9f --- /dev/null +++ b/basic_led.runs/impl_1/top_21544.backup.vdi @@ -0,0 +1,540 @@ +#----------------------------------------------------------- +# Vivado v2024.2 (64-bit) +# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024 +# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 +# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 +# Start of session at: Sat Apr 26 17:07:07 2025 +# Process ID : 21544 +# Current directory : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1 +# Command line : vivado.exe -log top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace +# Log file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top.vdi +# Journal file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1\vivado.jou +# Running On : rishiTUF +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26100 +# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12650H +# CPU Frequency : 2688 MHz +# CPU Physical cores : 10 +# CPU Logical cores : 16 +# Host memory : 16777 MB +# Swap memory : 15032 MB +# Total Virtual : 31809 MB +# Available Virtual : 10245 MB +#----------------------------------------------------------- +source top.tcl -notrace +Command: open_checkpoint D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top.dcp + +Starting open_checkpoint Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 443.277 ; gain = 5.199 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 844.723 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2024.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Read ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 939.426 ; gain = 0.000 +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +INFO: [Designutils 20-5722] Start Reading Physical Databases. +Reading placement. +Read Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1448.668 ; gain = 0.000 +Reading placer database... +Read Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1448.668 ; gain = 0.000 +Read PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1448.668 ; gain = 0.000 +Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1448.668 ; gain = 0.000 +Reading routing. +Read RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1448.668 ; gain = 0.000 +Read Physdb Files: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1448.668 ; gain = 0.000 +Restored from archive | CPU: 1.000000 secs | Memory: 0.000000 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1448.668 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1448.668 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Project 1-604] Checkpoint was created with Vivado v2024.2 (64-bit) build 5239630 +open_checkpoint: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1448.668 ; gain = 1018.328 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.570 . Memory (MB): peak = 1465.785 ; gain = 17.117 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1481.785 ; gain = 16.000 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1880.535 ; gain = 0.000 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Phase 1 Initialization | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1880.535 ; gain = 0.000 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1880.535 ; gain = 0.000 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Phase 2 Timer Update And Timing Data Collection | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1880.535 ; gain = 0.000 + +Phase 3 Retarget +INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 +INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Retarget | Checksum: 1e01b447d +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Constant propagation | Checksum: 1e01b447d +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 5 Sweep +INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Phase 5 Sweep | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Sweep | Checksum: 1e01b447d +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.076 . Memory (MB): peak = 1880.535 ; gain = 0.000 +BUFG optimization | Checksum: 1e01b447d +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Shift Register Optimization | Checksum: 1e01b447d +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 8 Post Processing Netlist +Phase 8 Post Processing Netlist | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.080 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Post Processing Netlist | Checksum: 1e01b447d +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Phase 9 Finalization + +Phase 9.1 Finalizing Design Cores and Updating Shapes +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.081 . Memory (MB): peak = 1880.535 ; gain = 0.000 + +Phase 9.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Phase 9.2 Verifying Netlist Connectivity | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.086 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Phase 9 Finalization | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.086 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.087 . Memory (MB): peak = 1880.535 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1880.535 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1880.535 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 1e01b447d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1880.535 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +INFO: [Vivado 12-24828] Executing command : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx +Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Vivado/2024.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_drc_opted.rpt. +report_drc completed successfully +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1880.535 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1880.535 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1880.535 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_opt.dcp' has been generated. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1881.887 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1cfab23ea + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1881.887 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1881.887 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1cfab23ea + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1882.754 ; gain = 0.867 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 20da2ef42 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.127 . Memory (MB): peak = 1882.754 ; gain = 0.867 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 20da2ef42 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.130 . Memory (MB): peak = 1882.754 ; gain = 0.867 +Phase 1 Placer Initialization | Checksum: 20da2ef42 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.130 . Memory (MB): peak = 1882.754 ; gain = 0.867 + +Phase 2 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1882.754 ; gain = 0.000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.134 . Memory (MB): peak = 1882.754 ; gain = 0.867 +INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed +Ending Placer Task | Checksum: 1cfab23ea + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.135 . Memory (MB): peak = 1882.754 ; gain = 0.867 +49 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel. +Running report generation with 2 threads. +INFO: [Vivado 12-24828] Executing command : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb +INFO: [Vivado 12-24828] Executing command : report_io -file top_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1882.754 ; gain = 0.000 +INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file top_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1882.754 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1886.445 ; gain = 0.012 +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1886.445 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1886.445 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1886.445 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1886.445 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1886.445 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1886.445 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_placed.dcp' has been generated. +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' + +Starting Initial Update Timing Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1886.445 ; gain = 0.000 +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +58 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1892.578 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1892.578 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1892.578 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1892.578 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1892.578 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1892.578 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1892.578 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: ea16cbba ConstDB: 0 ShapeSum: 4512fbd9 RouteDB: a0815c57 +Post Restoration Checksum: NetGraph: 1763e75d | NumContArr: b0cd464b | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 24d8322e2 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1972.848 ; gain = 78.250 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 24d8322e2 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1978.918 ; gain = 84.320 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 24d8322e2 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1978.918 ; gain = 84.320 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 1 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 1 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 24d8322e2 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 + +Phase 3 Global Routing +Phase 3 Global Routing | Checksum: 24d8322e2 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 + +Phase 4 Initial Routing + +Phase 4.1 Initial Net Routing Pass + Number of Nodes with overlaps = 0 +Phase 4.1 Initial Net Routing Pass | Checksum: 298c5947d + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 +Phase 4 Initial Routing | Checksum: 298c5947d + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 + +Phase 5 Rip-up And Reroute + +Phase 5.1 Global Iteration 0 +Phase 5.1 Global Iteration 0 | Checksum: 298c5947d + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 +Phase 5 Rip-up And Reroute | Checksum: 298c5947d + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 + +Phase 6 Delay and Skew Optimization +Phase 6 Delay and Skew Optimization | Checksum: 298c5947d + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 + +Phase 7 Post Hold Fix + +Phase 7.1 Hold Fix Iter +Phase 7.1 Hold Fix Iter | Checksum: 298c5947d + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 +Phase 7 Post Hold Fix | Checksum: 298c5947d + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.000637806 % + Global Horizontal Routing Utilization = 0.000130141 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +--GLOBAL Congestion: +Utilization threshold used for congestion level computation: 0.85 +Congestion Report +North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 5.40541%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 1.47059%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 8 Route finalize | Checksum: 298c5947d + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 298c5947d + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 298c5947d + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 + +Phase 11 Post Process Routing +Phase 11 Post Process Routing | Checksum: 298c5947d + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 +Total Elapsed time in route_design: 11.674 secs + +Phase 12 Post-Route Event Processing +Phase 12 Post-Route Event Processing | Checksum: 21c50984f + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 +INFO: [Route 35-16] Router Completed Successfully +Ending Routing Task | Checksum: 21c50984f + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 95.168 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +65 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1989.766 ; gain = 97.188 +INFO: [Vivado 12-24828] Executing command : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx +Command: report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_drc_routed.rpt. +report_drc completed successfully +INFO: [Vivado 12-24828] Executing command : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx +Command: report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Vivado 12-24838] Running report commands "report_incremental_reuse, report_route_status" in parallel. +Running report generation with 2 threads. +INFO: [Vivado 12-24828] Executing command : report_route_status -file top_route_status.rpt -pb top_route_status.pb +INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file top_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [Vivado 12-24828] Executing command : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx +Command: report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +82 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file top_clock_utilization_routed.rpt +INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2021.203 ; gain = 0.016 +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2021.203 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2021.203 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 2021.203 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2021.203 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2021.203 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2021.203 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_routed.dcp' has been generated. +INFO: [Common 17-206] Exiting Vivado at Sat Apr 26 17:07:43 2025... diff --git a/basic_led.runs/impl_1/top_22200.backup.vdi b/basic_led.runs/impl_1/top_22200.backup.vdi new file mode 100644 index 0000000..1886537 --- /dev/null +++ b/basic_led.runs/impl_1/top_22200.backup.vdi @@ -0,0 +1,635 @@ +#----------------------------------------------------------- +# Vivado v2024.2 (64-bit) +# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024 +# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 +# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 +# Start of session at: Sat Apr 26 17:40:35 2025 +# Process ID : 22200 +# Current directory : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1 +# Command line : vivado.exe -log top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace +# Log file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top.vdi +# Journal file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1\vivado.jou +# Running On : rishiTUF +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26100 +# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12650H +# CPU Frequency : 2688 MHz +# CPU Physical cores : 10 +# CPU Logical cores : 16 +# Host memory : 16777 MB +# Swap memory : 15032 MB +# Total Virtual : 31809 MB +# Available Virtual : 9305 MB +#----------------------------------------------------------- +source top.tcl -notrace +create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 656.090 ; gain = 226.457 +Command: link_design -top top -part xc7a35tcpg236-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 843.078 ; gain = 0.000 +INFO: [Project 1-479] Netlist was created with Vivado 2024.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc] +Finished Parsing XDC File [D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 969.918 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +5 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.335 . Memory (MB): peak = 992.352 ; gain = 18.375 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1477.633 ; gain = 485.281 + +Starting Logic Optimization Task + +Phase 1 Initialization + +Phase 1.1 Core Generation And Design Setup +Phase 1.1 Core Generation And Design Setup | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 1.2 Setup Constraints And Sort Netlist +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 1 Initialization | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2 Timer Update And Timing Data Collection + +Phase 2.1 Timer Update +Phase 2.1 Timer Update | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.2 Timing Data Collection +Phase 2.2 Timing Data Collection | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 2 Timer Update And Timing Data Collection | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3 Retarget +INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0 +INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0 +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 3 Retarget | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Retarget | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 4 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 4 Constant propagation | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Constant propagation | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 5 Sweep +INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 5 Sweep | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Sweep | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 6 BUFG optimization +Phase 6 BUFG optimization | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 1879.738 ; gain = 0.000 +BUFG optimization | Checksum: 236c74c94 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 7 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 7 Shift Register Optimization | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Shift Register Optimization | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 8 Post Processing Netlist +Phase 8 Post Processing Netlist | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Post Processing Netlist | Checksum: 236c74c94 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Phase 9 Finalization + +Phase 9.1 Finalizing Design Cores and Updating Shapes +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 9.2 Verifying Netlist Connectivity + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 9.2 Verifying Netlist Connectivity | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 9 Finalization | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + +Ending Logic Optimization Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 236c74c94 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1879.738 ; gain = 905.762 +INFO: [Vivado 12-24828] Executing command : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx +Command: report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Vivado/2024.2/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_drc_opted.rpt. +report_drc completed successfully +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 1879.738 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_opt.dcp' has been generated. +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-83] Releasing license: Implementation +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Starting Placer Task + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1cfab23ea + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1cfab23ea + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.2 Update Timing before SLR Path Opt +Phase 2.2 Update Timing before SLR Path Opt | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.3 Post-Processing in Floorplanning +Phase 2.3 Post-Processing in Floorplanning | Checksum: 295772899 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.4 Global Place Phase1 +Phase 2.4 Global Place Phase1 | Checksum: 229d9fc97 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.202 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 2.5 Global Place Phase2 +WARNING: [Place 46-29] Timing had been disabled during Placer and, therefore, physical synthesis in Placer will be skipped. +Phase 2.5 Global Place Phase2 | Checksum: 1fdc50950 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.224 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 2 Global Placement | Checksum: 1fdc50950 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.225 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1fdc50950 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.225 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 218f9ec8d + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.227 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 23324120f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.231 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 23324120f + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.232 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.400 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.400 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.401 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.401 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.415 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.417 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 4.3 Placer Reporting + +Phase 4.3.1 Print Estimated Congestion +INFO: [Place 30-612] Post-Placement Estimated Congestion + ____________________________________________________ +| | Global Congestion | Short Congestion | +| Direction | Region Size | Region Size | +|___________|___________________|___________________| +| North| 1x1| 1x1| +|___________|___________________|___________________| +| South| 1x1| 1x1| +|___________|___________________|___________________| +| East| 1x1| 1x1| +|___________|___________________|___________________| +| West| 1x1| 1x1| +|___________|___________________|___________________| + +Phase 4.3.1 Print Estimated Congestion | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.417 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 4.3 Placer Reporting | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.417 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1879.738 ; gain = 0.000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.417 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1b1073788 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.418 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Ending Placer Task | Checksum: 18f80c67c + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.418 . Memory (MB): peak = 1879.738 ; gain = 0.000 +44 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +INFO: [Vivado 12-24838] Running report commands "report_control_sets, report_io, report_utilization" in parallel. +Running report generation with 2 threads. +INFO: [Vivado 12-24828] Executing command : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb +INFO: [Vivado 12-24828] Executing command : report_control_sets -verbose -file top_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1879.738 ; gain = 0.000 +INFO: [Vivado 12-24828] Executing command : report_io -file top_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1879.738 ; gain = 0.000 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1886.414 ; gain = 0.000 +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1886.414 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1886.414 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_placed.dcp' has been generated. +Command: phys_opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' + +Starting Initial Update Timing Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1886.414 ; gain = 0.000 +INFO: [Vivado_Tcl 4-235] No timing constraint found. The netlist was not modified. +INFO: [Common 17-83] Releasing license: Implementation +53 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +phys_opt_design completed successfully +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.520 ; gain = 0.027 +INFO: [Timing 38-480] Writing timing data to binary archive. +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1894.520 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1894.520 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_physopt.dcp' has been generated. +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs + +Phase 1 Build RT Design +Checksum: PlaceDB: a9ec6e4c ConstDB: 0 ShapeSum: 4512fbd9 RouteDB: a0815c57 +Post Restoration Checksum: NetGraph: 94020b10 | NumContArr: 37e9989c | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1971.547 ; gain = 77.027 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1977.602 ; gain = 83.082 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1977.602 ; gain = 83.082 + +Router Utilization Summary + Global Vertical Routing Utilization = 0 % + Global Horizontal Routing Utilization = 0 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 2 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 2 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 2 Router Initialization | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 3 Global Routing +Phase 3 Global Routing | Checksum: 2513d98e6 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 4 Initial Routing + +Phase 4.1 Initial Net Routing Pass + Number of Nodes with overlaps = 0 +Phase 4.1 Initial Net Routing Pass | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +Phase 4 Initial Routing | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 5 Rip-up And Reroute + +Phase 5.1 Global Iteration 0 +Phase 5.1 Global Iteration 0 | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +Phase 5 Rip-up And Reroute | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 6 Delay and Skew Optimization +Phase 6 Delay and Skew Optimization | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 7 Post Hold Fix + +Phase 7.1 Hold Fix Iter +Phase 7.1 Hold Fix Iter | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +Phase 7 Post Hold Fix | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 8 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.000797257 % + Global Horizontal Routing Utilization = 0.000780843 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + (Failed Nets is the sum of unrouted and partially routed nets) + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + + +--GLOBAL Congestion: +Utilization threshold used for congestion level computation: 0.85 +Congestion Report +North Dir 1x1 Area, Max Cong = 0.900901%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 3.6036%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 1.47059%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 8 Route finalize | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 9 Verifying routed nets + + Verification completed successfully +Phase 9 Verifying routed nets | Checksum: 204669160 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 10 Depositing Routes +Phase 10 Depositing Routes | Checksum: 2ce2cc2fa + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Phase 11 Post Process Routing +Phase 11 Post Process Routing | Checksum: 2ce2cc2fa + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +Total Elapsed time in route_design: 11.471 secs + +Phase 12 Post-Route Event Processing +Phase 12 Post-Route Event Processing | Checksum: c68260c9 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +INFO: [Route 35-16] Router Completed Successfully +Ending Routing Task | Checksum: c68260c9 + +Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +60 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:11 . Memory (MB): peak = 1988.480 ; gain = 93.961 +INFO: [Vivado 12-24828] Executing command : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx +Command: report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_drc_routed.rpt. +report_drc completed successfully +INFO: [Vivado 12-24828] Executing command : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx +Command: report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [Vivado 12-24828] Executing command : report_timing_summary -max_paths 10 -report_unconstrained -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [Vivado 12-24838] Running report commands "report_incremental_reuse, report_route_status" in parallel. +Running report generation with 2 threads. +INFO: [Vivado 12-24828] Executing command : report_route_status -file top_route_status.rpt -pb top_route_status.pb +INFO: [Vivado 12-24828] Executing command : report_incremental_reuse -file top_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [Vivado 12-24828] Executing command : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx +Command: report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! Power estimation will be inaccurate until this is corrected. +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +77 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [Vivado 12-24828] Executing command : report_clock_utilization -file top_clock_utilization_routed.rpt +INFO: [Vivado 12-24828] Executing command : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Timing 38-480] Writing timing data to binary archive. +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2022.895 ; gain = 0.035 +Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 2022.895 ; gain = 0.000 +Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2022.895 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top_routed.dcp' has been generated. +INFO: [Common 17-206] Exiting Vivado at Sat Apr 26 17:41:08 2025... diff --git a/basic_led.runs/impl_1/top_bus_skew_routed.pb b/basic_led.runs/impl_1/top_bus_skew_routed.pb Binary files differnew file mode 100644 index 0000000..3390588 --- /dev/null +++ b/basic_led.runs/impl_1/top_bus_skew_routed.pb diff --git a/basic_led.runs/impl_1/top_bus_skew_routed.rpt b/basic_led.runs/impl_1/top_bus_skew_routed.rpt new file mode 100644 index 0000000..f703361 --- /dev/null +++ b/basic_led.runs/impl_1/top_bus_skew_routed.rpt @@ -0,0 +1,16 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024 +| Date : Sat Apr 26 17:41:08 2025 +| Host : rishiTUF running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file top_bus_skew_routed.rpt -pb top_bus_skew_routed.pb -rpx top_bus_skew_routed.rpx +| Design : top +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/basic_led.runs/impl_1/top_bus_skew_routed.rpx b/basic_led.runs/impl_1/top_bus_skew_routed.rpx Binary files differnew file mode 100644 index 0000000..633d16e --- /dev/null +++ b/basic_led.runs/impl_1/top_bus_skew_routed.rpx diff --git a/basic_led.runs/impl_1/top_clock_utilization_routed.rpt b/basic_led.runs/impl_1/top_clock_utilization_routed.rpt new file mode 100644 index 0000000..dc9f250 --- /dev/null +++ b/basic_led.runs/impl_1/top_clock_utilization_routed.rpt @@ -0,0 +1,93 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024 +| Date : Sat Apr 26 17:41:08 2025 +| Host : rishiTUF running 64-bit major release (build 9200) +| Command : report_clock_utilization -file top_clock_utilization_routed.rpt +| Design : top +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 0 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 72 | 0 | 0 | 0 | +| BUFIO | 0 | 20 | 0 | 0 | 0 | +| BUFMR | 0 | 10 | 0 | 0 | 0 | +| BUFR | 0 | 20 | 0 | 0 | 0 | +| MMCM | 0 | 5 | 0 | 0 | 0 | +| PLL | 0 | 5 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+ +* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered +** Non-Clock Loads column represents cell count of non-clock pin loads + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+ +* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered +** Non-Clock Loads column represents cell count of non-clock pin loads + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1200 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1500 | 0 | 450 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1800 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 950 | 0 | 300 | 0 | 10 | 0 | 5 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y2 | 0 | 0 | +| Y1 | 0 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports diff --git a/basic_led.runs/impl_1/top_control_sets_placed.rpt b/basic_led.runs/impl_1/top_control_sets_placed.rpt new file mode 100644 index 0000000..f124976 --- /dev/null +++ b/basic_led.runs/impl_1/top_control_sets_placed.rpt @@ -0,0 +1,77 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024 +| Date : Sat Apr 26 17:40:55 2025 +| Host : rishiTUF running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file top_control_sets_placed.rpt +| Design : top +| Device : xc7a35t +--------------------------------------------------------------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Total control sets | 0 | +| Minimum number of control sets | 0 | +| Addition due to synthesis replication | 0 | +| Addition due to physical synthesis replication | 0 | +| Unused register locations in slices containing registers | 0 | ++----------------------------------------------------------+-------+ +* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers +** Run report_qor_suggestions for automated merging and remapping suggestions + + +2. Histogram +------------ + ++--------------------+-------+ +| Fanout | Count | ++--------------------+-------+ +| Total control sets | 0 | +| >= 0 to < 4 | 0 | +| >= 4 to < 6 | 0 | +| >= 6 to < 8 | 0 | +| >= 8 to < 10 | 0 | +| >= 10 to < 12 | 0 | +| >= 12 to < 14 | 0 | +| >= 14 to < 16 | 0 | +| >= 16 | 0 | ++--------------------+-------+ +* Control sets can be remapped at either synth_design or opt_design + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 0 | 0 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++--------------+---------------+------------------+------------------+----------------+--------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | ++--------------+---------------+------------------+------------------+----------------+--------------+ + + diff --git a/basic_led.runs/impl_1/top_drc_opted.pb b/basic_led.runs/impl_1/top_drc_opted.pb Binary files differnew file mode 100644 index 0000000..8ebaa78 --- /dev/null +++ b/basic_led.runs/impl_1/top_drc_opted.pb diff --git a/basic_led.runs/impl_1/top_drc_opted.rpt b/basic_led.runs/impl_1/top_drc_opted.rpt new file mode 100644 index 0000000..46486fa --- /dev/null +++ b/basic_led.runs/impl_1/top_drc_opted.rpt @@ -0,0 +1,35 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024 +| Date : Sat Apr 26 17:40:54 2025 +| Host : rishiTUF running 64-bit major release (build 9200) +| Command : report_drc -file top_drc_opted.rpt -pb top_drc_opted.pb -rpx top_drc_opted.rpx +| Design : top +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: <entire design considered> + Ruledeck: default + Max checks: <unlimited> + Checks found: 0 ++------+----------+-------------+--------+ +| Rule | Severity | Description | Checks | ++------+----------+-------------+--------+ ++------+----------+-------------+--------+ + +2. REPORT DETAILS +----------------- + diff --git a/basic_led.runs/impl_1/top_drc_opted.rpx b/basic_led.runs/impl_1/top_drc_opted.rpx Binary files differnew file mode 100644 index 0000000..b8185cd --- /dev/null +++ b/basic_led.runs/impl_1/top_drc_opted.rpx diff --git a/basic_led.runs/impl_1/top_drc_routed.pb b/basic_led.runs/impl_1/top_drc_routed.pb Binary files differnew file mode 100644 index 0000000..8ebaa78 --- /dev/null +++ b/basic_led.runs/impl_1/top_drc_routed.pb diff --git a/basic_led.runs/impl_1/top_drc_routed.rpt b/basic_led.runs/impl_1/top_drc_routed.rpt new file mode 100644 index 0000000..052cbe0 --- /dev/null +++ b/basic_led.runs/impl_1/top_drc_routed.rpt @@ -0,0 +1,35 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024 +| Date : Sat Apr 26 17:41:07 2025 +| Host : rishiTUF running 64-bit major release (build 9200) +| Command : report_drc -file top_drc_routed.rpt -pb top_drc_routed.pb -rpx top_drc_routed.rpx +| Design : top +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Fully Routed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: <entire design considered> + Ruledeck: default + Max checks: <unlimited> + Checks found: 0 ++------+----------+-------------+--------+ +| Rule | Severity | Description | Checks | ++------+----------+-------------+--------+ ++------+----------+-------------+--------+ + +2. REPORT DETAILS +----------------- + diff --git a/basic_led.runs/impl_1/top_drc_routed.rpx b/basic_led.runs/impl_1/top_drc_routed.rpx Binary files differnew file mode 100644 index 0000000..f96211b --- /dev/null +++ b/basic_led.runs/impl_1/top_drc_routed.rpx diff --git a/basic_led.runs/impl_1/top_io_placed.rpt b/basic_led.runs/impl_1/top_io_placed.rpt new file mode 100644 index 0000000..7617fd9 --- /dev/null +++ b/basic_led.runs/impl_1/top_io_placed.rpt @@ -0,0 +1,280 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024 +| Date : Sat Apr 26 17:40:55 2025 +| Host : rishiTUF running 64-bit major release (build 9200) +| Command : report_io -file top_io_placed.rpt +| Design : top +| Device : xc7a35t +| Speed File : -1 +| Package : cpg236 +| Package Version : FINAL 2014-02-19 +| Package Pin Delay Version : VERS. 2.0 2014-02-19 +---------------------------------------------------------------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 2 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A2 | | | MGTPTXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| A3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A4 | | | MGTPRXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTPRXN1_216 | Gigabit | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | | MGTREFCLK0N_216 | Gigabit | | | | | | | | | | | | | | | | +| A9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A10 | | | MGTREFCLK1N_216 | Gigabit | | | | | | | | | | | | | | | | +| A11 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| A12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| A13 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A17 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| A18 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| A19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B1 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| B2 | | | MGTPTXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | MGTPRXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B6 | | | MGTPRXP1_216 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B8 | | | MGTREFCLK0P_216 | Gigabit | | | | | | | | | | | | | | | | +| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B10 | | | MGTREFCLK1P_216 | Gigabit | | | | | | | | | | | | | | | | +| B11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| B12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| B13 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| B14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B15 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B19 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| C2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C5 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C7 | | | MGTRREF_216 | Gigabit | | | | | | | | | | | | | | | | +| C8 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| C9 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C11 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| C12 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| C13 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| C14 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C15 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C16 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C17 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| C18 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | | | MGTPTXN0_216 | Gigabit | | | | | | | | | | | | | | | | +| D2 | | | MGTPTXP0_216 | Gigabit | | | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D17 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| D18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| D19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| E1 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| E3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| E19 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| F1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F3 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| F17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| F18 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| F19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G2 | | High Range | IO_L1N_T0_AD4N_35 | User IO | | 35 | | | | | | | | | | | | | | +| G3 | | High Range | IO_L1P_T0_AD4P_35 | User IO | | 35 | | | | | | | | | | | | | | +| G7 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | | +| G13 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G17 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| G19 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| H1 | | High Range | IO_L3P_T0_DQS_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H2 | | High Range | IO_L2P_T0_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H9 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| H10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H17 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| H18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H19 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| J1 | | High Range | IO_L3N_T0_DQS_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J2 | | High Range | IO_L2N_T0_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | | +| J3 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | | +| J7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| J17 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| J18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| J19 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| K1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| K2 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | | +| K3 | | High Range | IO_L7N_T1_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | | +| K7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| K8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| K13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| K17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| L2 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | | +| L3 | | High Range | IO_L8P_T1_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | | +| L7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| L17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| L18 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| L19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | | +| M2 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | | +| M3 | | High Range | IO_L8N_T1_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | | +| M7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| M8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| M12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| M18 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| M19 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | | +| N2 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | | +| N3 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| N7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| N8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| N9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| P1 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | | +| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | | +| P17 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| P19 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| R2 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| R17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| R18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| R19 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| T17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| T18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| T19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U5 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U7 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| U8 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U10 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| U11 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| U12 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| U13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | 3.30 | | | | | | | | | +| U14 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| U15 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| U16 | switch | High Range | IO_L23N_T3_A02_D18_14 | INPUT | LVCMOS33 | 14 | | | | NONE | | FIXED | | | | NONE | | | | +| U17 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| U19 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| V1 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V2 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | | +| V7 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| V8 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | | +| V10 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| V11 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | | +| V12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| V13 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| V14 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| V15 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| V16 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| V17 | led | High Range | IO_L19N_T3_A09_D25_VREF_14 | OUTPUT | LVCMOS33 | 14 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| V18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V19 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| W1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W2 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| W3 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| W4 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W6 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W7 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| W9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| W10 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| W11 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W13 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| W14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| W15 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| W16 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| W17 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| W18 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| W19 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | ++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/basic_led.runs/impl_1/top_methodology_drc_routed.pb b/basic_led.runs/impl_1/top_methodology_drc_routed.pb Binary files differnew file mode 100644 index 0000000..210b56b --- /dev/null +++ b/basic_led.runs/impl_1/top_methodology_drc_routed.pb diff --git a/basic_led.runs/impl_1/top_methodology_drc_routed.rpt b/basic_led.runs/impl_1/top_methodology_drc_routed.rpt new file mode 100644 index 0000000..f98be85 --- /dev/null +++ b/basic_led.runs/impl_1/top_methodology_drc_routed.rpt @@ -0,0 +1,34 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024 +| Date : Sat Apr 26 17:41:08 2025 +| Host : rishiTUF running 64-bit major release (build 9200) +| Command : report_methodology -file top_methodology_drc_routed.rpt -pb top_methodology_drc_routed.pb -rpx top_methodology_drc_routed.rpx +| Design : top +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Fully Routed +----------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: <entire design considered> + Max checks: <unlimited> + Checks found: 0 ++------+----------+-------------+--------+ +| Rule | Severity | Description | Checks | ++------+----------+-------------+--------+ ++------+----------+-------------+--------+ + +2. REPORT DETAILS +----------------- + diff --git a/basic_led.runs/impl_1/top_methodology_drc_routed.rpx b/basic_led.runs/impl_1/top_methodology_drc_routed.rpx Binary files differnew file mode 100644 index 0000000..349c24a --- /dev/null +++ b/basic_led.runs/impl_1/top_methodology_drc_routed.rpx diff --git a/basic_led.runs/impl_1/top_opt.dcp b/basic_led.runs/impl_1/top_opt.dcp Binary files differnew file mode 100644 index 0000000..2a72e86 --- /dev/null +++ b/basic_led.runs/impl_1/top_opt.dcp diff --git a/basic_led.runs/impl_1/top_physopt.dcp b/basic_led.runs/impl_1/top_physopt.dcp Binary files differnew file mode 100644 index 0000000..32081ca --- /dev/null +++ b/basic_led.runs/impl_1/top_physopt.dcp diff --git a/basic_led.runs/impl_1/top_placed.dcp b/basic_led.runs/impl_1/top_placed.dcp Binary files differnew file mode 100644 index 0000000..19b8713 --- /dev/null +++ b/basic_led.runs/impl_1/top_placed.dcp diff --git a/basic_led.runs/impl_1/top_power_routed.rpt b/basic_led.runs/impl_1/top_power_routed.rpt new file mode 100644 index 0000000..007e3e0 --- /dev/null +++ b/basic_led.runs/impl_1/top_power_routed.rpt @@ -0,0 +1,140 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024 +| Date : Sat Apr 26 17:41:08 2025 +| Host : rishiTUF running 64-bit major release (build 9200) +| Command : report_power -file top_power_routed.rpt -pb top_power_summary_routed.pb -rpx top_power_routed.rpx +| Design : top +| Device : xc7a35tcpg236-1 +| Design State : routed +| Grade : commercial +| Process : typical +| Characterization : Production +------------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.814 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.740 | +| Device Static (W) | 0.073 | +| Effective TJA (C/W) | 5.0 | +| Max Ambient (C) | 80.9 | +| Junction Temperature (C) | 29.1 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts> + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.002 | 1 | --- | --- | +| LUT as Logic | 0.002 | 1 | 20800 | <0.01 | +| Signals | 0.006 | 2 | --- | --- | +| I/O | 0.733 | 2 | 106 | 1.89 | +| Static Power | 0.073 | | | | +| Total | 0.814 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ +| Vccint | 1.000 | 0.023 | 0.012 | 0.011 | NA | Unspecified | NA | +| Vccaux | 1.800 | 0.039 | 0.027 | 0.013 | NA | Unspecified | NA | +| Vcco33 | 3.300 | 0.207 | 0.206 | 0.001 | NA | Unspecified | NA | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA | ++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 5.0 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.6 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++------+-----------+ +| Name | Power (W) | ++------+-----------+ +| top | 0.740 | ++------+-----------+ + + diff --git a/basic_led.runs/impl_1/top_power_routed.rpx b/basic_led.runs/impl_1/top_power_routed.rpx Binary files differnew file mode 100644 index 0000000..e63356d --- /dev/null +++ b/basic_led.runs/impl_1/top_power_routed.rpx diff --git a/basic_led.runs/impl_1/top_power_summary_routed.pb b/basic_led.runs/impl_1/top_power_summary_routed.pb Binary files differnew file mode 100644 index 0000000..2cc9329 --- /dev/null +++ b/basic_led.runs/impl_1/top_power_summary_routed.pb diff --git a/basic_led.runs/impl_1/top_route_status.pb b/basic_led.runs/impl_1/top_route_status.pb Binary files differnew file mode 100644 index 0000000..c0a6644 --- /dev/null +++ b/basic_led.runs/impl_1/top_route_status.pb diff --git a/basic_led.runs/impl_1/top_route_status.rpt b/basic_led.runs/impl_1/top_route_status.rpt new file mode 100644 index 0000000..7c06581 --- /dev/null +++ b/basic_led.runs/impl_1/top_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 4 : + # of nets not needing routing.......... : 2 : + # of internally routed nets........ : 2 : + # of routable nets..................... : 2 : + # of fully routed nets............. : 2 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/basic_led.runs/impl_1/top_routed.dcp b/basic_led.runs/impl_1/top_routed.dcp Binary files differnew file mode 100644 index 0000000..e0e69b7 --- /dev/null +++ b/basic_led.runs/impl_1/top_routed.dcp diff --git a/basic_led.runs/impl_1/top_timing_summary_routed.pb b/basic_led.runs/impl_1/top_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/basic_led.runs/impl_1/top_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4’)Timing analysis from Implemented netlist.
\ No newline at end of file diff --git a/basic_led.runs/impl_1/top_timing_summary_routed.rpt b/basic_led.runs/impl_1/top_timing_summary_routed.rpt new file mode 100644 index 0000000..b47b3c7 --- /dev/null +++ b/basic_led.runs/impl_1/top_timing_summary_routed.rpt @@ -0,0 +1,272 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024 +| Date : Sat Apr 26 17:41:08 2025 +| Host : rishiTUF running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -report_unconstrained -file top_timing_summary_routed.rpt -pb top_timing_summary_routed.pb -rpx top_timing_summary_routed.rpx -warn_on_violation +| Design : top +| Device : 7a35t-cpg236 +| Speed File : -1 PRODUCTION 1.23 2018-06-13 +| Design State : Routed +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : No + Borrow Time for Max Delay Exceptions : Yes + Merge Timing Exceptions : Yes + Inter-SLR Compensation : Conservative + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + +------------------------------------------------------------------------------------------------ +| Report Methodology +| ------------------ +------------------------------------------------------------------------------------------------ + +No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock (0) +2. checking constant_clock (0) +3. checking pulse_width_clock (0) +4. checking unconstrained_internal_endpoints (0) +5. checking no_input_delay (0) +6. checking no_output_delay (0) +7. checking multiple_clock (0) +8. checking generated_clocks (0) +9. checking loops (0) +10. checking partial_input_delay (0) +11. checking partial_output_delay (0) +12. checking latch_loops (0) + +1. checking no_clock (0) +------------------------ + There are 0 register/latch pins with no clock. + + +2. checking constant_clock (0) +------------------------------ + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock (0) +--------------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints (0) +------------------------------------------------ + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay (0) +------------------------------ + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay (0) +------------------------------- + There are 0 ports with no output delay specified. + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock (0) +------------------------------ + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks (0) +-------------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops (0) +--------------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay (0) +------------------------------------ + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay (0) +------------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops (0) +---------------------------- + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + inf 0.000 0 1 inf 0.000 0 1 NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| User Ignored Path Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- + + +------------------------------------------------------------------------------------------------ +| Unconstrained Path Table +| ------------------------ +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock +---------- ---------- -------- +(none) + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +-------------------------------------------------------------------------------------- +Path Group: (none) +From Clock: + To Clock: + +Max Delay 1 Endpoint +Min Delay 1 Endpoint +-------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: switch + (input port) + Destination: led + (output port) + Path Group: (none) + Path Type: Max at Slow Process Corner + Data Path Delay: 8.367ns (logic 5.082ns (60.731%) route 3.286ns (39.269%)) + Logic Levels: 3 (IBUF=1 LUT1=1 OBUF=1) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + U16 0.000 0.000 f switch (IN) + net (fo=0) 0.000 0.000 switch + U16 IBUF (Prop_ibuf_I_O) 1.450 1.450 f switch_IBUF_inst/O + net (fo=1, routed) 1.577 3.027 switch_IBUF + SLICE_X0Y7 LUT1 (Prop_lut1_I0_O) 0.124 3.151 r led_OBUF_inst_i_1/O + net (fo=1, routed) 1.709 4.860 led_OBUF + V17 OBUF (Prop_obuf_I_O) 3.508 8.367 r led_OBUF_inst/O + net (fo=0) 0.000 8.367 led + V17 r led (OUT) + ------------------------------------------------------------------- ------------------- + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack: inf + Source: switch + (input port) + Destination: led + (output port) + Path Group: (none) + Path Type: Min at Fast Process Corner + Data Path Delay: 2.433ns (logic 1.472ns (60.505%) route 0.961ns (39.495%)) + Logic Levels: 3 (IBUF=1 LUT1=1 OBUF=1) + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + U16 0.000 0.000 f switch (IN) + net (fo=0) 0.000 0.000 switch + U16 IBUF (Prop_ibuf_I_O) 0.218 0.218 f switch_IBUF_inst/O + net (fo=1, routed) 0.610 0.828 switch_IBUF + SLICE_X0Y7 LUT1 (Prop_lut1_I0_O) 0.045 0.873 r led_OBUF_inst_i_1/O + net (fo=1, routed) 0.351 1.224 led_OBUF + V17 OBUF (Prop_obuf_I_O) 1.209 2.433 r led_OBUF_inst/O + net (fo=0) 0.000 2.433 led + V17 r led (OUT) + ------------------------------------------------------------------- ------------------- + + + + + diff --git a/basic_led.runs/impl_1/top_timing_summary_routed.rpx b/basic_led.runs/impl_1/top_timing_summary_routed.rpx Binary files differnew file mode 100644 index 0000000..7337fed --- /dev/null +++ b/basic_led.runs/impl_1/top_timing_summary_routed.rpx diff --git a/basic_led.runs/impl_1/top_utilization_placed.pb b/basic_led.runs/impl_1/top_utilization_placed.pb Binary files differnew file mode 100644 index 0000000..a14e917 --- /dev/null +++ b/basic_led.runs/impl_1/top_utilization_placed.pb diff --git a/basic_led.runs/impl_1/top_utilization_placed.rpt b/basic_led.runs/impl_1/top_utilization_placed.rpt new file mode 100644 index 0000000..664467a --- /dev/null +++ b/basic_led.runs/impl_1/top_utilization_placed.rpt @@ -0,0 +1,207 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024 +| Date : Sat Apr 26 17:40:55 2025 +| Host : rishiTUF running 64-bit major release (build 9200) +| Command : report_utilization -file top_utilization_placed.rpt -pb top_utilization_placed.pb +| Design : top +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Fully Placed +--------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs | 1 | 0 | 0 | 20800 | <0.01 | +| LUT as Logic | 1 | 0 | 0 | 20800 | <0.01 | +| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+------------+-----------+-------+ +* Warning! LUT value is adjusted to account for LUT combining. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++------------------------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------------------------------------+------+-------+------------+-----------+-------+ +| Slice | 1 | 0 | 0 | 8150 | 0.01 | +| SLICEL | 1 | 0 | | | | +| SLICEM | 0 | 0 | | | | +| LUT as Logic | 1 | 0 | 0 | 20800 | <0.01 | +| using O5 output only | 0 | | | | | +| using O6 output only | 1 | | | | | +| using O5 and O6 | 0 | | | | | +| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | | +| using O5 output only | 0 | | | | | +| using O6 output only | 0 | | | | | +| using O5 and O6 | 0 | | | | | +| LUT as Shift Register | 0 | 0 | | | | +| using O5 output only | 0 | | | | | +| using O6 output only | 0 | | | | | +| using O5 and O6 | 0 | | | | | +| Slice Registers | 0 | 0 | 0 | 41600 | 0.00 | +| Register driven from within the Slice | 0 | | | | | +| Register driven from outside the Slice | 0 | | | | | +| Unique Control Sets | 0 | | 0 | 8150 | 0.00 | ++------------------------------------------+------+-------+------------+-----------+-------+ +* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------+------+-------+------------+-----------+-------+ +| DSPs | 0 | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+------------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 2 | 2 | 0 | 106 | 1.89 | +| IOB Master Pads | 0 | | | | | +| IOB Slave Pads | 2 | | | | | +| Bonded IPADs | 0 | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+------------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 0 | 20 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+-------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+------------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 1 | IO | +| LUT1 | 1 | LUT | +| IBUF | 1 | IO | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/basic_led.runs/impl_1/vivado.jou b/basic_led.runs/impl_1/vivado.jou new file mode 100644 index 0000000..c15b5d2 --- /dev/null +++ b/basic_led.runs/impl_1/vivado.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2024.2 (64-bit) +# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024 +# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 +# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 +# Start of session at: Sat Apr 26 17:41:55 2025 +# Process ID : 14724 +# Current directory : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1 +# Command line : vivado.exe -log top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace +# Log file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top.vdi +# Journal file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1\vivado.jou +# Running On : rishiTUF +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26100 +# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12650H +# CPU Frequency : 2688 MHz +# CPU Physical cores : 10 +# CPU Logical cores : 16 +# Host memory : 16777 MB +# Swap memory : 15032 MB +# Total Virtual : 31809 MB +# Available Virtual : 9479 MB +#----------------------------------------------------------- +source top.tcl -notrace diff --git a/basic_led.runs/impl_1/vivado.pb b/basic_led.runs/impl_1/vivado.pb Binary files differnew file mode 100644 index 0000000..2756d3f --- /dev/null +++ b/basic_led.runs/impl_1/vivado.pb diff --git a/basic_led.runs/impl_1/vivado_21544.backup.jou b/basic_led.runs/impl_1/vivado_21544.backup.jou new file mode 100644 index 0000000..a4f8d48 --- /dev/null +++ b/basic_led.runs/impl_1/vivado_21544.backup.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2024.2 (64-bit) +# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024 +# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 +# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 +# Start of session at: Sat Apr 26 17:07:07 2025 +# Process ID : 21544 +# Current directory : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1 +# Command line : vivado.exe -log top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace +# Log file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top.vdi +# Journal file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1\vivado.jou +# Running On : rishiTUF +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26100 +# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12650H +# CPU Frequency : 2688 MHz +# CPU Physical cores : 10 +# CPU Logical cores : 16 +# Host memory : 16777 MB +# Swap memory : 15032 MB +# Total Virtual : 31809 MB +# Available Virtual : 10245 MB +#----------------------------------------------------------- +source top.tcl -notrace diff --git a/basic_led.runs/impl_1/vivado_22200.backup.jou b/basic_led.runs/impl_1/vivado_22200.backup.jou new file mode 100644 index 0000000..3ba5ff8 --- /dev/null +++ b/basic_led.runs/impl_1/vivado_22200.backup.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2024.2 (64-bit) +# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024 +# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 +# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 +# Start of session at: Sat Apr 26 17:40:35 2025 +# Process ID : 22200 +# Current directory : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1 +# Command line : vivado.exe -log top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source top.tcl -notrace +# Log file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1/top.vdi +# Journal file : D:/verilog_prog/bink/basic_led/basic_led.runs/impl_1\vivado.jou +# Running On : rishiTUF +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26100 +# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12650H +# CPU Frequency : 2688 MHz +# CPU Physical cores : 10 +# CPU Logical cores : 16 +# Host memory : 16777 MB +# Swap memory : 15032 MB +# Total Virtual : 31809 MB +# Available Virtual : 9305 MB +#----------------------------------------------------------- +source top.tcl -notrace diff --git a/basic_led.runs/impl_1/write_bitstream.pb b/basic_led.runs/impl_1/write_bitstream.pb Binary files differnew file mode 100644 index 0000000..3fb8321 --- /dev/null +++ b/basic_led.runs/impl_1/write_bitstream.pb diff --git a/basic_led.runs/synth_1/.Vivado_Synthesis.queue.rst b/basic_led.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/basic_led.runs/synth_1/.Vivado_Synthesis.queue.rst diff --git a/basic_led.runs/synth_1/.Xil/top_propImpl.xdc b/basic_led.runs/synth_1/.Xil/top_propImpl.xdc new file mode 100644 index 0000000..4950986 --- /dev/null +++ b/basic_led.runs/synth_1/.Xil/top_propImpl.xdc @@ -0,0 +1,5 @@ +set_property SRC_FILE_INFO {cfile:D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc rfile:../../../basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc id:1} [current_design] +set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {led}] +set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {switch}] diff --git a/basic_led.runs/synth_1/.vivado.begin.rst b/basic_led.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..2c03648 --- /dev/null +++ b/basic_led.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ +<?xml version="1.0"?> +<ProcessHandle Version="1" Minor="0"> + <Process Command="vivado.bat" Owner="rishi" Host="RISHITUF" Pid="29184" HostCore="16" HostMemory="016777072640"> + </Process> +</ProcessHandle> diff --git a/basic_led.runs/synth_1/.vivado.end.rst b/basic_led.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/basic_led.runs/synth_1/.vivado.end.rst diff --git a/basic_led.runs/synth_1/ISEWrap.js b/basic_led.runs/synth_1/ISEWrap.js new file mode 100644 index 0000000..61806d0 --- /dev/null +++ b/basic_led.runs/synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) { + if ( ISEScriptArgs(loopi) == "-quiet" ) { + ISELogEcho = false; + break; + } + } + + // 4. WSH version check + var ISEOptimalVersionWSH = 5.6; + var ISECurrentVersionWSH = WScript.Version; + if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) { + + ISEStdErr( "" ); + ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " + + ISEOptimalVersionWSH + " or higher. Downloads" ); + ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " ); + ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" ); + ISEStdErr( "" ); + + ISEOldVersionWSH = true; + } + +} + +function ISEStep( ISEProg, ISEArgs ) { + + // CHECK for a STOP FILE + if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) { + ISEStdErr( "" ); + ISEStdErr( "*** Halting run - EA reset detected ***" ); + ISEStdErr( "" ); + WScript.Quit( 1 ); + } + + // WRITE STEP HEADER to LOG + ISEStdOut( "" ); + ISEStdOut( "*** Running " + ISEProg ); + ISEStdOut( " with args " + ISEArgs ); + ISEStdOut( "" ); + + // LAUNCH! + var ISEExitCode = ISEExec( ISEProg, ISEArgs ); + if ( ISEExitCode != 0 ) { + WScript.Quit( ISEExitCode ); + } + +} + +function ISEExec( ISEProg, ISEArgs ) { + + var ISEStep = ISEProg; + if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") { + ISEProg += ".bat"; + } + + var ISECmdLine = ISEProg + " " + ISEArgs; + var ISEExitCode = 1; + + if ( ISEOldVersionWSH ) { // WSH 5.1 + + // BEGIN file creation + ISETouchFile( ISEStep, "begin" ); + + // LAUNCH! + ISELogFileStr.Close(); + ISECmdLine = + "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" ); + ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" ); + ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg + + "\" Owner=\"" + ISEUser + + "\" Host=\"" + ISEHost + + "\" Pid=\"" + ISEPid + + "\" HostCore=\"" + ISEHOSTCORE + + "\" HostMemory=\"" + ISEMEMTOTAL + + "\">" ); + ISEBeginFile.WriteLine( " </Process>" ); + ISEBeginFile.WriteLine( "</ProcessHandle>" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/basic_led.runs/synth_1/ISEWrap.sh b/basic_led.runs/synth_1/ISEWrap.sh new file mode 100644 index 0000000..05d5381 --- /dev/null +++ b/basic_led.runs/synth_1/ISEWrap.sh @@ -0,0 +1,85 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. +# + +cmd_exists() +{ + command -v "$1" >/dev/null 2>&1 +} + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! + +HostNameFile=/proc/sys/kernel/hostname +if cmd_exists hostname +then +ISE_HOST=$(hostname) +elif cmd_exists uname +then +ISE_HOST=$(uname -n) +elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] +then +ISE_HOST=$(cat $HostNameFile) +elif [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi + +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE +echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE +echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE +echo " </Process>" >> $ISE_BEGINFILE +echo "</ProcessHandle>" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/basic_led.runs/synth_1/__synthesis_is_complete__ b/basic_led.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/basic_led.runs/synth_1/__synthesis_is_complete__ diff --git a/basic_led.runs/synth_1/gen_run.xml b/basic_led.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..ab355c8 --- /dev/null +++ b/basic_led.runs/synth_1/gen_run.xml @@ -0,0 +1,59 @@ +<?xml version="1.0" encoding="UTF-8"?> +<GenRun Id="synth_1" LaunchPart="xc7a35tcpg236-1" LaunchTime="1745669381" LaunchIncrCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp"> + <File Type="PA-TCL" Name="top.tcl"/> + <File Type="REPORTS-TCL" Name="top_reports.tcl"/> + <File Type="RDS-RDS" Name="top.vds"/> + <File Type="RDS-PROPCONSTRS" Name="top_drc_synth.rpt"/> + <File Type="RDS-UTIL" Name="top_utilization_synth.rpt"/> + <File Type="RDS-UTIL-PB" Name="top_utilization_synth.pb"/> + <File Type="RDS-DCP" Name="top.dcp"/> + <File Type="VDS-TIMINGSUMMARY" Name="top_timing_summary_synth.rpt"/> + <File Type="VDS-TIMING-PB" Name="top_timing_summary_synth.pb"/> + <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sources_1/new/top.v"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="top"/> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> + <Filter Type="Constrs"/> + <File Path="$PSRCDIR/constrs_1/new/switches_leds_constarins.xdc"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + </FileInfo> + </File> + <Config> + <Option Name="ConstrsType" Val="XDC"/> + </Config> + </FileSet> + <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> + <Filter Type="Utils"/> + <File Path="$PSRCDIR/utils_1/imports/synth_1/top.dcp"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedInSteps" Val="synth_1"/> + <Attr Name="AutoDcp" Val="1"/> + </FileInfo> + </File> + <Config> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"> + <Desc>Vivado Synthesis Defaults</Desc> + </StratHandle> + <Step Id="synth_design"/> + </Strategy> +</GenRun> diff --git a/basic_led.runs/synth_1/htr.txt b/basic_led.runs/synth_1/htr.txt new file mode 100644 index 0000000..8dec13b --- /dev/null +++ b/basic_led.runs/synth_1/htr.txt @@ -0,0 +1,10 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +REM Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +REM + +vivado -log top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl diff --git a/basic_led.runs/synth_1/incr_synth_reason.pb b/basic_led.runs/synth_1/incr_synth_reason.pb new file mode 100644 index 0000000..4cb4ed4 --- /dev/null +++ b/basic_led.runs/synth_1/incr_synth_reason.pb @@ -0,0 +1 @@ +Â 6No compile time benefit to using incremental synthesis
\ No newline at end of file diff --git a/basic_led.runs/synth_1/project.wdf b/basic_led.runs/synth_1/project.wdf new file mode 100644 index 0000000..7e4d6ea --- /dev/null +++ b/basic_led.runs/synth_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6239663732653931616461373438353561373136613632656165333934353835:506172656e742050412070726f6a656374204944:00 +eof:2383876863 diff --git a/basic_led.runs/synth_1/rundef.js b/basic_led.runs/synth_1/rundef.js new file mode 100644 index 0000000..725c265 --- /dev/null +++ b/basic_led.runs/synth_1/rundef.js @@ -0,0 +1,37 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "D:/Vitis/2024.2/bin;D:/Vivado/2024.2/ids_lite/ISE/bin/nt64;D:/Vivado/2024.2/ids_lite/ISE/lib/nt64;D:/Vivado/2024.2/bin;"; +} else { + PathVal = "D:/Vitis/2024.2/bin;D:/Vivado/2024.2/ids_lite/ISE/bin/nt64;D:/Vivado/2024.2/ids_lite/ISE/lib/nt64;D:/Vivado/2024.2/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/basic_led.runs/synth_1/runme.bat b/basic_led.runs/synth_1/runme.bat new file mode 100644 index 0000000..6733dc9 --- /dev/null +++ b/basic_led.runs/synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +rem Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/basic_led.runs/synth_1/runme.log b/basic_led.runs/synth_1/runme.log new file mode 100644 index 0000000..c361a71 --- /dev/null +++ b/basic_led.runs/synth_1/runme.log @@ -0,0 +1,213 @@ + +*** Running vivado + with args -log top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl + + + +****** Vivado v2024.2 (64-bit) + **** SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024 + **** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 + **** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 + **** Start of session at: Sat Apr 26 17:39:43 2025 + ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. + ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. + +source top.tcl -notrace +create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 654.832 ; gain = 225.449 +Command: read_checkpoint -auto_incremental -incremental D:/verilog_prog/bink/basic_led/basic_led.srcs/utils_1/imports/synth_1/top.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from D:/verilog_prog/bink/basic_led/basic_led.srcs/utils_1/imports/synth_1/top.dcp for incremental synthesis +INFO: [Vivado 12-7989] Please ensure there are no constraint changes +Command: synth_design -top top -part xc7a35tcpg236-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 10784 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1309.051 ; gain = 467.340 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'top' [D:/verilog_prog/bink/basic_led/basic_led.srcs/sources_1/new/top.v:4] +INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [D:/verilog_prog/bink/basic_led/basic_led.srcs/sources_1/new/top.v:4] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1412.879 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc] +Finished Parsing XDC File [D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1412.879 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1412.879 ; gain = 0.000 +INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1438.098 ; gain = 596.387 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1599.168 ; gain = 757.457 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1599.168 ; gain = 757.457 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1608.746 ; gain = 767.035 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT1 | 1| +|2 |IBUF | 1| +|3 |OBUF | 1| ++------+-----+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1825.883 ; gain = 984.172 +Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1827.273 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1830.961 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete | Checksum: 671c28aa +INFO: [Common 17-83] Releasing license: Synthesis +21 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1830.961 ; gain = 1171.859 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1830.961 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1/top.dcp' has been generated. +INFO: [Vivado 12-24828] Executing command : report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sat Apr 26 17:40:13 2025... diff --git a/basic_led.runs/synth_1/runme.sh b/basic_led.runs/synth_1/runme.sh new file mode 100644 index 0000000..8b10950 --- /dev/null +++ b/basic_led.runs/synth_1/runme.sh @@ -0,0 +1,44 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=D:/Vitis/2024.2/bin;D:/Vivado/2024.2/ids_lite/ISE/bin/nt64;D:/Vivado/2024.2/ids_lite/ISE/lib/nt64:D:/Vivado/2024.2/bin +else + PATH=D:/Vitis/2024.2/bin;D:/Vivado/2024.2/ids_lite/ISE/bin/nt64;D:/Vivado/2024.2/ids_lite/ISE/lib/nt64:D:/Vivado/2024.2/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl diff --git a/basic_led.runs/synth_1/top.dcp b/basic_led.runs/synth_1/top.dcp Binary files differnew file mode 100644 index 0000000..2682370 --- /dev/null +++ b/basic_led.runs/synth_1/top.dcp diff --git a/basic_led.runs/synth_1/top.tcl b/basic_led.runs/synth_1/top.tcl new file mode 100644 index 0000000..f7f0577 --- /dev/null +++ b/basic_led.runs/synth_1/top.tcl @@ -0,0 +1,112 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +namespace eval ::optrace { + variable script "D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1/top.tcl" + variable category "vivado_synth" +} + +# Try to connect to running dispatch if we haven't done so already. +# This code assumes that the Tcl interpreter is not using threads, +# since the ::dispatch::connected variable isn't mutex protected. +if {![info exists ::dispatch::connected]} { + namespace eval ::dispatch { + variable connected false + if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { + set result "true" + if {[catch { + if {[lsearch -exact [package names] DispatchTcl] < 0} { + set result [load librdi_cd_clienttcl[info sharedlibextension]] + } + if {$result eq "false"} { + puts "WARNING: Could not load dispatch client library" + } + set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] + if { $connect_id eq "" } { + puts "WARNING: Could not initialize dispatch client" + } else { + puts "INFO: Dispatch client connection id - $connect_id" + set connected true + } + } catch_res]} { + puts "WARNING: failed to connect to dispatch server - $catch_res" + } + } + } +} +if {$::dispatch::connected} { + # Remove the dummy proc if it exists. + if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { + rename ::OPTRACE "" + } + proc ::OPTRACE { task action {tags {} } } { + ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category + } + # dispatch is generic. We specifically want to attach logging. + ::vitis_log::connect_client +} else { + # Add dummy proc if it doesn't exist. + if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { + proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { + # Do nothing + } + } +} + +OPTRACE "synth_1" START { ROLLUP_AUTO } +set_param chipscope.maxJobs 4 +set_param xicom.use_bs_reader 1 +OPTRACE "Creating in-memory project" START { } +create_project -in_memory -part xc7a35tcpg236-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir D:/verilog_prog/bink/basic_led/basic_led.cache/wt [current_project] +set_property parent.project_path D:/verilog_prog/bink/basic_led/basic_led.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property board_part digilentinc.com:basys3:part0:1.2 [current_project] +set_property ip_output_repo d:/verilog_prog/bink/basic_led/basic_led.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +OPTRACE "Creating in-memory project" END { } +OPTRACE "Adding files" START { } +read_verilog -library xil_defaultlib D:/verilog_prog/bink/basic_led/basic_led.srcs/sources_1/new/top.v +OPTRACE "Adding files" END { } +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc +set_property used_in_implementation false [get_files D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc] + +set_param ips.enableIPCacheLiteLoad 1 + +read_checkpoint -auto_incremental -incremental D:/verilog_prog/bink/basic_led/basic_led.srcs/utils_1/imports/synth_1/top.dcp +close [open __synthesis_is_running__ w] + +OPTRACE "synth_design" START { } +synth_design -top top -part xc7a35tcpg236-1 +OPTRACE "synth_design" END { } +if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } { + send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING" +} + + +OPTRACE "write_checkpoint" START { CHECKPOINT } +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef top.dcp +OPTRACE "write_checkpoint" END { } +OPTRACE "synth reports" START { REPORT } +generate_parallel_reports -reports { "report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb" } +OPTRACE "synth reports" END { } +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] +OPTRACE "synth_1" END { } diff --git a/basic_led.runs/synth_1/top.vds b/basic_led.runs/synth_1/top.vds new file mode 100644 index 0000000..52b4db4 --- /dev/null +++ b/basic_led.runs/synth_1/top.vds @@ -0,0 +1,222 @@ +#----------------------------------------------------------- +# Vivado v2024.2 (64-bit) +# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024 +# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 +# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 +# Start of session at: Sat Apr 26 17:39:43 2025 +# Process ID : 23896 +# Current directory : D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1 +# Command line : vivado.exe -log top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl +# Log file : D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1/top.vds +# Journal file : D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1\vivado.jou +# Running On : rishiTUF +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26100 +# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12650H +# CPU Frequency : 2688 MHz +# CPU Physical cores : 10 +# CPU Logical cores : 16 +# Host memory : 16777 MB +# Swap memory : 15032 MB +# Total Virtual : 31809 MB +# Available Virtual : 9180 MB +#----------------------------------------------------------- +source top.tcl -notrace +create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 654.832 ; gain = 225.449 +Command: read_checkpoint -auto_incremental -incremental D:/verilog_prog/bink/basic_led/basic_led.srcs/utils_1/imports/synth_1/top.dcp +INFO: [Vivado 12-5825] Read reference checkpoint from D:/verilog_prog/bink/basic_led/basic_led.srcs/utils_1/imports/synth_1/top.dcp for incremental synthesis +INFO: [Vivado 12-7989] Please ensure there are no constraint changes +Command: synth_design -top top -part xc7a35tcpg236-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' +INFO: [Device 21-403] Loading part xc7a35tcpg236-1 +INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} +INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. +INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes +INFO: [Synth 8-7075] Helper process launched with PID 10784 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1309.051 ; gain = 467.340 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'top' [D:/verilog_prog/bink/basic_led/basic_led.srcs/sources_1/new/top.v:4] +INFO: [Synth 8-6155] done synthesizing module 'top' (0#1) [D:/verilog_prog/bink/basic_led/basic_led.srcs/sources_1/new/top.v:4] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1412.879 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc] +Finished Parsing XDC File [D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/verilog_prog/bink/basic_led/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/top_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1412.879 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1412.879 ; gain = 0.000 +INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run +INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7a35tcpg236-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1412.879 ; gain = 571.168 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 90 (col length:60) +BRAMs: 100 (col length: RAMB18 60 RAMB36 30) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +WARNING: [Synth 8-7080] Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1438.098 ; gain = 596.387 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1599.168 ; gain = 757.457 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1599.168 ; gain = 757.457 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 1608.746 ; gain = 767.035 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT1 | 1| +|2 |IBUF | 1| +|3 |OBUF | 1| ++------+-----+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 1825.883 ; gain = 984.172 +Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1825.883 ; gain = 984.172 +INFO: [Project 1-571] Translating synthesized netlist +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1827.273 ; gain = 0.000 +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1830.961 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Synth Design complete | Checksum: 671c28aa +INFO: [Common 17-83] Releasing license: Synthesis +21 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 1830.961 ; gain = 1171.859 +Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1830.961 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1/top.dcp' has been generated. +INFO: [Vivado 12-24828] Executing command : report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sat Apr 26 17:40:13 2025... diff --git a/basic_led.runs/synth_1/top_utilization_synth.pb b/basic_led.runs/synth_1/top_utilization_synth.pb Binary files differnew file mode 100644 index 0000000..a14e917 --- /dev/null +++ b/basic_led.runs/synth_1/top_utilization_synth.pb diff --git a/basic_led.runs/synth_1/top_utilization_synth.rpt b/basic_led.runs/synth_1/top_utilization_synth.rpt new file mode 100644 index 0000000..97a95b6 --- /dev/null +++ b/basic_led.runs/synth_1/top_utilization_synth.rpt @@ -0,0 +1,176 @@ +Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024 +| Date : Sat Apr 26 17:40:13 2025 +| Host : rishiTUF running 64-bit major release (build 9200) +| Command : report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb +| Design : top +| Device : xc7a35tcpg236-1 +| Speed File : -1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs* | 1 | 0 | 0 | 20800 | <0.01 | +| LUT as Logic | 1 | 0 | 0 | 20800 | <0.01 | +| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 | +| Slice Registers | 0 | 0 | 0 | 41600 | 0.00 | +| Register as Flip Flop | 0 | 0 | 0 | 41600 | 0.00 | +| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 | +| F7 Muxes | 0 | 0 | 0 | 16300 | 0.00 | +| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 | ++-------------------------+------+-------+------------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. +Warning! LUT value is adjusted to account for LUT combining. +Warning! For any ECO changes, please run place_design if there are unplaced instances + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------+------+-------+------------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+------------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------+------+-------+------------+-----------+-------+ +| DSPs | 0 | 0 | 0 | 90 | 0.00 | ++-----------+------+-------+------------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-----------------------------+------+-------+------------+-----------+-------+ +| Bonded IOB | 2 | 0 | 0 | 106 | 1.89 | +| Bonded IPADs | 0 | 0 | 0 | 10 | 0.00 | +| Bonded OPADs | 0 | 0 | 0 | 4 | 0.00 | +| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 | +| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 | +| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 | +| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 | +| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 | +| IBUFDS | 0 | 0 | 0 | 104 | 0.00 | +| GTPE2_CHANNEL | 0 | 0 | 0 | 2 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 0 | 106 | 0.00 | +| OLOGIC | 0 | 0 | 0 | 106 | 0.00 | ++-----------------------------+------+-------+------------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++------------+------+-------+------------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 0 | 20 | 0.00 | +| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 | +| PLLE2_ADV | 0 | 0 | 0 | 5 | 0.00 | +| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 | +| BUFHCE | 0 | 0 | 0 | 72 | 0.00 | +| BUFR | 0 | 0 | 0 | 20 | 0.00 | ++------------+------+-------+------------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++-------------+------+-------+------------+-----------+-------+ +| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+------------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 1 | IO | +| LUT1 | 1 | LUT | +| IBUF | 1 | IO | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/basic_led.runs/synth_1/vivado.jou b/basic_led.runs/synth_1/vivado.jou new file mode 100644 index 0000000..73d026c --- /dev/null +++ b/basic_led.runs/synth_1/vivado.jou @@ -0,0 +1,24 @@ +#----------------------------------------------------------- +# Vivado v2024.2 (64-bit) +# SW Build 5239630 on Fri Nov 08 22:35:27 MST 2024 +# IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024 +# SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024 +# Start of session at: Sat Apr 26 17:39:43 2025 +# Process ID : 23896 +# Current directory : D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1 +# Command line : vivado.exe -log top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source top.tcl +# Log file : D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1/top.vds +# Journal file : D:/verilog_prog/bink/basic_led/basic_led.runs/synth_1\vivado.jou +# Running On : rishiTUF +# Platform : Windows Server 2016 or Windows 10 +# Operating System : 26100 +# Processor Detail : 12th Gen Intel(R) Core(TM) i7-12650H +# CPU Frequency : 2688 MHz +# CPU Physical cores : 10 +# CPU Logical cores : 16 +# Host memory : 16777 MB +# Swap memory : 15032 MB +# Total Virtual : 31809 MB +# Available Virtual : 9180 MB +#----------------------------------------------------------- +source top.tcl -notrace diff --git a/basic_led.runs/synth_1/vivado.pb b/basic_led.runs/synth_1/vivado.pb Binary files differnew file mode 100644 index 0000000..e3e7b6e --- /dev/null +++ b/basic_led.runs/synth_1/vivado.pb diff --git a/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc b/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc new file mode 100644 index 0000000..b7ab74f --- /dev/null +++ b/basic_led.srcs/constrs_1/new/switches_leds_constarins.xdc @@ -0,0 +1,8 @@ +## Configuration for Bank 0 +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] + +## LED +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports {led}] +## SWITCH +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports {switch}] diff --git a/basic_led.srcs/sources_1/new/top.v b/basic_led.srcs/sources_1/new/top.v new file mode 100644 index 0000000..790ccec --- /dev/null +++ b/basic_led.srcs/sources_1/new/top.v @@ -0,0 +1,11 @@ +`timescale 1ns / 1ps + + +module top( + input switch, + output led +); + +assign led = ~switch; + +endmodule diff --git a/basic_led.srcs/utils_1/imports/synth_1/top.dcp b/basic_led.srcs/utils_1/imports/synth_1/top.dcp Binary files differnew file mode 100644 index 0000000..14f793d --- /dev/null +++ b/basic_led.srcs/utils_1/imports/synth_1/top.dcp diff --git a/basic_led.xpr b/basic_led.xpr new file mode 100644 index 0000000..4f89bd2 --- /dev/null +++ b/basic_led.xpr @@ -0,0 +1,236 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- Product Version: Vivado v2024.2 (64-bit) --> +<!-- --> +<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. --> +<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. --> + +<Project Product="Vivado" Version="7" Minor="68" Path="D:/verilog_prog/bink/basic_led/basic_led.xpr"> + <DefaultLaunch Dir="$PRUNDIR"/> + <Configuration> + <Option Name="Id" Val="b9f72e91ada74855a716a62eae394585"/> + <Option Name="Part" Val="xc7a35tcpg236-1"/> + <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> + <Option Name="CompiledLibDirXSim" Val=""/> + <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> + <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/> + <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/> + <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/> + <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/> + <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/> + <Option Name="SimulatorInstallDirModelSim" Val=""/> + <Option Name="SimulatorInstallDirQuesta" Val=""/> + <Option Name="SimulatorInstallDirXcelium" Val=""/> + <Option Name="SimulatorInstallDirVCS" Val=""/> + <Option Name="SimulatorInstallDirRiviera" Val=""/> + <Option Name="SimulatorInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorGccInstallDirModelSim" Val=""/> + <Option Name="SimulatorGccInstallDirQuesta" Val=""/> + <Option Name="SimulatorGccInstallDirXcelium" Val=""/> + <Option Name="SimulatorGccInstallDirVCS" Val=""/> + <Option Name="SimulatorGccInstallDirRiviera" Val=""/> + <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/> + <Option Name="SimulatorVersionXsim" Val="2024.2"/> + <Option Name="SimulatorVersionModelSim" Val="2024.1"/> + <Option Name="SimulatorVersionQuesta" Val="2024.1"/> + <Option Name="SimulatorVersionXcelium" Val="24.03.003"/> + <Option Name="SimulatorVersionVCS" Val="V-2023.12-SP1"/> + <Option Name="SimulatorVersionRiviera" Val="2024.04"/> + <Option Name="SimulatorVersionActiveHdl" Val="15.0"/> + <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/> + <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/> + <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/> + <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/> + <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/> + <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/> + <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/> + <Option Name="BoardPart" Val="digilentinc.com:basys3:part0:1.2"/> + <Option Name="ActiveSimSet" Val="sim_1"/> + <Option Name="DefaultLib" Val="xil_defaultlib"/> + <Option Name="ProjectType" Val="Default"/> + <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> + <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/> + <Option Name="IPCachePermission" Val="read"/> + <Option Name="IPCachePermission" Val="write"/> + <Option Name="EnableCoreContainer" Val="FALSE"/> + <Option Name="EnableResourceEstimation" Val="FALSE"/> + <Option Name="SimCompileState" Val="TRUE"/> + <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> + <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> + <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> + <Option Name="EnableBDX" Val="FALSE"/> + <Option Name="DSABoardId" Val="basys3"/> + <Option Name="WTXSimLaunchSim" Val="0"/> + <Option Name="WTModelSimLaunchSim" Val="0"/> + <Option Name="WTQuestaLaunchSim" Val="0"/> + <Option Name="WTIesLaunchSim" Val="0"/> + <Option Name="WTVcsLaunchSim" Val="0"/> + <Option Name="WTRivieraLaunchSim" Val="0"/> + <Option Name="WTActivehdlLaunchSim" Val="0"/> + <Option Name="WTXSimExportSim" Val="0"/> + <Option Name="WTModelSimExportSim" Val="0"/> + <Option Name="WTQuestaExportSim" Val="0"/> + <Option Name="WTIesExportSim" Val="0"/> + <Option Name="WTVcsExportSim" Val="0"/> + <Option Name="WTRivieraExportSim" Val="0"/> + <Option Name="WTActivehdlExportSim" Val="0"/> + <Option Name="GenerateIPUpgradeLog" Val="TRUE"/> + <Option Name="XSimRadix" Val="hex"/> + <Option Name="XSimTimeUnit" Val="ns"/> + <Option Name="XSimArrayDisplayLimit" Val="1024"/> + <Option Name="XSimTraceLimit" Val="65536"/> + <Option Name="SimTypes" Val="rtl"/> + <Option Name="SimTypes" Val="bfm"/> + <Option Name="SimTypes" Val="tlm"/> + <Option Name="SimTypes" Val="tlm_dpi"/> + <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/> + <Option Name="DcpsUptoDate" Val="TRUE"/> + <Option Name="UseInlineHdlIP" Val="TRUE"/> + <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/> + </Configuration> + <FileSets Version="1" Minor="32"> + <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> + <Filter Type="Srcs"/> + <File Path="$PSRCDIR/sources_1/new/top.v"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="top"/> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1"> + <Filter Type="Constrs"/> + <File Path="$PSRCDIR/constrs_1/new/switches_leds_constarins.xdc"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + </FileInfo> + </File> + <Config> + <Option Name="ConstrsType" Val="XDC"/> + </Config> + </FileSet> + <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> + <Config> + <Option Name="DesignMode" Val="RTL"/> + <Option Name="TopModule" Val="top"/> + <Option Name="TopLib" Val="xil_defaultlib"/> + <Option Name="TopAutoSet" Val="TRUE"/> + <Option Name="TransportPathDelay" Val="0"/> + <Option Name="TransportIntDelay" Val="0"/> + <Option Name="SelectedSimModel" Val="rtl"/> + <Option Name="PamDesignTestbench" Val=""/> + <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/> + <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/> + <Option Name="PamPseudoTop" Val="pseudo_tb"/> + <Option Name="SrcSet" Val="sources_1"/> + <Option Name="CosimPdi" Val=""/> + <Option Name="CosimPlatform" Val=""/> + <Option Name="CosimElf" Val=""/> + </Config> + </FileSet> + <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1"> + <Filter Type="Utils"/> + <File Path="$PSRCDIR/utils_1/imports/synth_1/top.dcp"> + <FileInfo> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="implementation"/> + <Attr Name="UsedInSteps" Val="synth_1"/> + <Attr Name="AutoDcp" Val="1"/> + </FileInfo> + </File> + <Config> + <Option Name="TopAutoSet" Val="TRUE"/> + </Config> + </FileSet> + </FileSets> + <Simulators> + <Simulator Name="XSim"> + <Option Name="Description" Val="Vivado Simulator"/> + <Option Name="CompiledLib" Val="0"/> + </Simulator> + <Simulator Name="ModelSim"> + <Option Name="Description" Val="ModelSim Simulator"/> + </Simulator> + <Simulator Name="Questa"> + <Option Name="Description" Val="Questa Advanced Simulator"/> + </Simulator> + <Simulator Name="Riviera"> + <Option Name="Description" Val="Riviera-PRO Simulator"/> + </Simulator> + <Simulator Name="ActiveHDL"> + <Option Name="Description" Val="Active-HDL Simulator"/> + </Simulator> + </Simulators> + <Runs Version="1" Minor="22"> + <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"> + <Desc>Vivado Synthesis Defaults</Desc> + </StratHandle> + <Step Id="synth_design"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 8 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true"> + <Strategy Version="1" Minor="2"> + <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"> + <Desc>Default settings for Implementation.</Desc> + </StratHandle> + <Step Id="init_design"/> + <Step Id="opt_design"/> + <Step Id="power_opt_design"/> + <Step Id="place_design"/> + <Step Id="post_place_power_opt_design"/> + <Step Id="phys_opt_design"/> + <Step Id="route_design"/> + <Step Id="post_route_phys_opt_design"/> + <Step Id="write_bitstream"/> + </Strategy> + <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> + <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/> + <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> + <RQSFiles/> + </Run> + </Runs> + <Board> + <Jumpers/> + </Board> + <DashboardSummary Version="1" Minor="0"> + <Dashboards> + <Dashboard Name="default_dashboard"> + <Gadgets> + <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/> + </Gadget> + <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/> + </Gadget> + <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/> + </Gadget> + <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/> + </Gadget> + <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0"> + <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/> + <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/> + <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/> + </Gadget> + <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1"> + <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/> + </Gadget> + </Gadgets> + </Dashboard> + <CurrentDashboard>default_dashboard</CurrentDashboard> + </Dashboards> + </DashboardSummary> +</Project> |